INTERDIGITATED BACK CONTACT METAL-INSULATOR-SEMICONDUCTOR SOLAR CELL WITH PRINTED OXIDE TUNNEL JUNCTIONS

• US 20180320821A1
• Filed: 06/08/2018
• Published: 11/08/2018
• Est. Priority Date: 12/20/2016
• Status: Active Grant

• Current Assignee: Zhejiang Kaiying New Materials Co., Ltd.
• Original Assignee: Zhejiang Kaiying New Materials Co., Ltd.
• Inventors: Hilali, Mohamed M.
• Granted Patent: US 10,670,187 B2
• Time in Patent Office: Days
• CPC Class Codes: F17C 2201/0109 with exteriorly curved end-piece
• CPC Class Codes: F17C 2201/0157 Polygonal
• CPC Class Codes: F17C 2201/052 large (>1000 m3)
• CPC Class Codes: F17C 2203/012 on or in the wall, e.g. ribs
• CPC Class Codes: F17C 2221/033 Methane, e.g. natural gas, CNG, LNG, GNL, GNC, PLNG
• CPC Class Codes: F17C 2223/0161 cryogenic, e.g. LNG, GNL, PLNG
• CPC Class Codes: F17C 2270/01 for fluid transport or storage
• CPC Class Codes: F17C 3/02 with provision for thermal insulation thermal insulation in general F16L59/00 ; refrigerators F25D; insulation specially adapted for cryogenic vessels F17C13/001; tank vehicles B60P3/22; railway tank wagons B61D5/00
• CPC Class Codes: H01L 31/022441 Electrode arrangements specially adapted for back-contact solar cells
• CPC Class Codes: H01L 31/02363 of the semiconductor body itself, e.g. textured active layers
• CPC Class Codes: H01L 31/035272 characterised by at least one potential jump barrier or surface barrier
• CPC Class Codes: H01L 31/03529 Shape of the potential jump barrier or surface barrier
• CPC Class Codes: H01L 31/0682 back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
• CPC Class Codes: H01L 31/072 the potential barriers being only of the PN heterojunction type
• CPC Class Codes: H01L 31/18 Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells

Abstract

Screen-printable metallization pastes for forming thin oxide tunnel junctions on the back-side surface of solar cells are disclosed. Interdigitated metal contacts can be deposited on the oxide tunnel junctions to provide all-back metal contact to a solar cell.

Claims

1. A semiconductor device interconnect comprising:

a silicon surface comprising a first region and a second region;

a positively-charged oxide layer overlying the first region;

a negatively-charged oxide layer overlying the second region;

a positive electrode grid overlying the positively-charged oxide layer; and

a negative electrode grid overlying the negatively-charged oxide layer.

2. The interconnect of claim 1, wherein the positively-charged oxide layer comprises a silicon oxide.

3. The interconnect of claim 1, wherein the positively-charged oxide layer comprises silicon dioxide.

4. The interconnect of claim 1, wherein the negatively-charged oxide layer comprises an aluminum oxide.

5. The interconnect of claim 1, wherein the positively-charged oxide layer comprises aluminum dioxide.

6. The interconnect of claim 1, wherein each of the positively-charged oxide layer and the negatively-charged oxide layer are characterized by a thickness from 1 Å

to 45 Å

.

7. The interconnect of claim 1, wherein each of the positive electrode grid and the negative electrode grid comprise copper particles, copper alloy particles, silver particles, silver alloy particles, or a combination of any of the foregoing.

8. The interconnect of claim 1, wherein each of the positive electrode grid and the negative electrode grid comprise a metallic glass.

9. The interconnect of claim 8, wherein the metallic glass comprises ZrCuNiAl, CuZr, CuZrAl, CuZrAg, CuZrAlAg, CuZrAlAgNi, CuZrAlNi, ZrTiNbCuNiAl, MgZn, MgCu, MgNi, MgNiY, MgCa, AlNiYLa, AlMg, AlMgCa, TiZrCuNi, NiNbZrTiPt, AlNiLa, ZrCuTiNiBe, MgCuYAg, AlLiCu, AlYFe, AgMgCa, AgMgCaCu, or a combination of any of the foregoing.

10. The interconnect of claim 8, wherein the metallic glass comprises copper, zirconium, aluminum, silver, nickel, or a combination of any of the foregoing.

11. The silicon layer of claim 8, wherein the metallic glass comprises an amorphous content from 50 wt % to about 99.9 wt %, wherein wt % is based on a total weight of the metallic glass.

12. The interconnect of claim 8, wherein the metallic glass comprises a crystalline content from 1 wt % to 50 wt %, where wt % is based on a total weight of the metallic glass.

13. The interconnect of claim 8, wherein the metallic glass has a resistivity from 2μ

Ω

-cm to about 1000 μ

Ω

-cm.

14. The interconnect of claim 1, wherein each of the positive electrode and the negative electrode comprise metallic glass-coated particles.

15. The interconnect of claim 14, wherein metallic glass-coated particles have an average particle diameter from 1 nm to 1000 nm.

16. The interconnect of claim 1, wherein each of the positive electrode and the negative electrode comprise metallic glass-coated silver particles, metallic glass-coated silver particles, or a combination thereof.

17. The interconnect of claim 1, wherein the surface comprises n-type silicon.

18. The interconnect of claim 1, wherein the surface comprises p-type silicon.

19. The interconnect of claim 1, wherein each of the positive electrode grid and the negative electrode grid comprise silver particles, silver alloy particles, silver coated with a metallic glass, a silver alloy coated with a metallic glass, copper particles, copper alloy particles, copper coated with a metallic glass, a copper alloy coated with a metallic glass, or a combination of any of the foregoing.

20. A silicon substrate comprising the interconnect of claim 1.

21. A semiconductor device comprising the interconnect of claim 1.

22. A semiconductor device comprising an interconnect, wherein the semiconductor interconnect is formed by a method comprising:

screen printing a positively charged dielectric paste on a first region of a back surface of a silicon substrate, wherein the positively charged dielectric paste comprises a positively charged silicon oxide;

screen printing a negatively charged dielectric paste on a second region of the back surface of the silicon substrate, wherein the negatively charged dielectric paste comprises a negatively charged aluminum oxide;

curing the positively charged dielectric paste and the negatively charged dielectric paste under conditions sufficient to form positively charged oxide tunnel junctions and negatively charged oxide tunnel junctions;

screen printing a first gridline metallization paste on the positively charged oxide tunnel junctions;

screen printing a second gridline metallization paste on the negatively charged oxide tunnel junctions; and

firing the first gridline metallization paste and the second gridline metallization paste to form a positive electrode and a negative electrode,

wherein each of the first gridline metallization paste and the second gridline metallization paste comprises;

a metal selected from copper, silver, or a combination thereof; and

a metallic glass, a non-oxide glass, or a combination thereof.

23. A semiconductor device comprising an interconnect, wherein the semiconductor interconnect is formed by a method comprising:

screen printing a positively-charged silicon oxide layer on a first region of a silicon substrate and forming a positively charged oxide tunnel junction on the first region of the silicon substrate, wherein the positively-charged silicon oxide layer comprises a doped silicon oxide;

screen printing a negatively-charged aluminum oxide layer on a second region of the semiconductor device and forming a negatively charged oxide tunnel junction on the second region the silicon substrate, wherein the negatively-charged silicon oxide layer comprises a doped aluminum oxide;

forming a positive electrode on the positively charged oxide tunnel junction; and

forming a negative electrode on the negatively charged oxide tunnel junction.