METHOD OF CONTROLLING ON-DIE TERMINATION AND SYSTEM PERFORMING THE SAME

• US 20180342274A1
• Filed: 03/12/2018
• Published: 11/29/2018
• Est. Priority Date: 05/29/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: SON, YOUNG-HOON, KIM, SI-HONG, LEE, CHANG-KYO, CHOI, JUNG-HWAN, HA, KYUNG-SOO
• Granted Patent: US 10,566,038 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: H03H 7/38 Impedance-matching networks

Abstract

A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

Claims

1. A method of controlling on-die termination (ODT) in a multi-rank memory system including a plurality of memory ranks, the method comprising:

enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank memory system is powered on;

enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and

disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

2. The method of claim 1, wherein each of the ODT circuits of the plurality of memory ranks has a first resistance value in the initial state.

3. The method of claim 2, wherein enabling the ODT circuits during the write operation comprises:

maintaining the ODT circuits of the plurality of memory ranks in the initial state to have the first resistance value during the write operation.

4. The method of claim 2, wherein enabling the ODT circuits during the write operation further comprises:

changing a resistance value of the ODT circuit of the write target memory rank from the first resistance value to a second resistance value different from the first resistance value during the write operation.

5. The method of claim 2, wherein enabling the ODT circuit of non-target memory ranks during the read operation comprises:

maintaining the ODT circuits of the non-target memory ranks in the initial state to have the first resistance value during the read operation.

6. The method of claim 1, wherein the ODT circuits of the plurality of memory ranks are configured to terminate data input-output pins of the plurality of memory ranks.

7. The method of claim 6, wherein the ODT circuits of the plurality of memory ranks maintain the initial state even while a data input-output operation through the data input-output pins is not performed.

8. The method of claim 1, wherein the ODT circuits of the non-target memory ranks among the plurality of memory ranks except the write target memory rank or the read target memory rank have a constant resistance value regardless of a memory access command from a memory controller.

9. The method of claim 8, wherein the constant resistance value of the non-target memory ranks is determined based on a value stored in a mode register of the multi-rank memory system.

10. The method of claim 1, wherein a resistance value of the ODT circuit of the write target memory rank is set to be equal to a resistance value of the ODT circuits of the non-target memory ranks among the plurality of memory ranks except the write target memory rank.

11. The method of claim 1, wherein a resistance value of the ODT circuit of the write target memory rank is set to be different from a resistance value of the ODT circuits of the non-target memory ranks among the plurality of memory ranks except the write target memory rank.

12. The method of claim 11, wherein the resistance value of the ODT circuit of the write target memory rank is set to be greater than the resistance value of the ODT circuits of the non-target memory ranks.

13. The method of claim 1, wherein the write target memory rank or the read target memory rank is converted from a power-down mode to a normal operation mode to perform the write operation or the read operation, and the non-target memory ranks among the plurality of memory ranks except the write target memory rank or the read target memory rank maintain the power-down mode during the write operation or the read operation.

14. A system comprising:

a plurality of memory ranks including a plurality of memory devices; and

a memory controller configured to control the plurality of memory ranks,

wherein on die termination (ODT) circuits of the plurality of memory ranks are enabled into an initial state when the system is powered on, the ODT circuits of the plurality of memory ranks are enabled during a write operation with respect to a write target memory rank and non-target memory ranks among the plurality of memory ranks, and the ODT circuit of a read target memory rank among the plurality of memory ranks is disabled while the ODT circuits of non-target memory ranks among the plurality of memory ranks are enabled during a read operation.

15. The system of claim 14, wherein the ODT circuits of the non-target memory ranks among the plurality of memory ranks except the write target memory rank or the read target memory rank have a constant resistance value regardless of a memory access command from the memory controller.

16. A system comprising:

a first memory rank comprising a plurality of first memory devices connected to a first on die termination (ODT) circuit; and

a second memory rank comprising a plurality of second memory devices connected to a second ODT circuit,

wherein the first and second ODT circuits are enabled during a write operation of the first memory rank, and the first ODT circuit is disabled and the second ODT circuit is enabled during a read operation of the first memory rank.

17. The system of claim 16, wherein each enabled ODT circuit provides termination impedance to a transmission line coupled to a data input-output pin of the corresponding memory rank.

18. The system of claim 17, wherein the first ODT circuit is disabled during the read operation only while read data corresponding to the read operation is output from the data input-output pin.

19. The system of claim 16, wherein a resistance value of the first ODT circuit is set to be equal to a resistance value of the second ODT circuit during the write operation.

20. The system of claim 16, wherein a resistance value of the first ODT circuit is set to be different from a resistance value of the second ODT circuit during the write operation.