APPARATUSES AND METHODS TO CONTROL MEMORY OPERATIONS ON BUFFERS
First Claim
Patent Images
1. An apparatus, comprising:
- a memory device including a buffer and an array of memory cells, wherein the buffer includes a plurality of caches; and
a host including a system controller, the system controller configured to control performance of a memory operation on data in the buffer, wherein the memory operation is associated with data movement among the plurality of caches.
7 Assignments
0 Petitions
Accused Products
Abstract
The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.
6 Citations
25 Claims
-
1. An apparatus, comprising:
-
a memory device including a buffer and an array of memory cells, wherein the buffer includes a plurality of caches; and a host including a system controller, the system controller configured to control performance of a memory operation on data in the buffer, wherein the memory operation is associated with data movement among the plurality of caches. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. An apparatus, comprising:
-
a host configured to issue commands; and a memory device including a buffer and an array of memory cells; and
wherein;the memory device is configured to perform a memory operation on data in the buffer responsive to receipt of a command from the host; and the buffer includes a plurality of first caches coupled to a second cache and the second cache coupled to the host via an input/output (I/O) line. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
-
-
19. A method, comprising:
-
receiving, from an external controller, a command to a memory device comprising an array of memory cells and a buffer; and responsive to receiving the command from the external controller, performing a memory operation on data in the buffer such that the buffer is available as a memory resource to the external controller; wherein the external controller is located internal to a host such that the host is further configured to control performing the memory operation on the data in the buffer. - View Dependent Claims (20, 21, 22, 23, 24, 25)
-
Specification