TFT SUBSTRATE AND METHOD FOR MAKING SAME

• US 20180374960A1
• Filed: 12/06/2016
• Published: 12/27/2018
• Est. Priority Date: 12/16/2015
• Status: Active Grant

• Current Assignee: Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. (Hon Hai Precision Industry Co., Ltd.), Hon Hai Precision Industry Co., Ltd.
• Original Assignee: Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. (Hon Hai Precision Industry Co., Ltd.), Hon Hai Precision Industry Co., Ltd.
• Inventors: KAO, YI-CHUN, SHIH, PO-LI, CHANG, WEI-CHIH, WU, I-WEI
• Granted Patent: US 10,749,039 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02491 Conductive materials
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: H01L 21/465 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/469
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/1213 : the pixel elements being TFTs

Abstract

A high-performance TFT substrate (100) for a flat panel display includes a substrate (110), a first conductive layer (130) on the substrate (110), a semiconductor layer (103) positioned on the first conductive layer (130), and a second conductive layer (150) positioned on the semiconductor layer (103). The first conductive layer (130) defines a gate electrode (101). The second conductive layer (150) defines a source electrode (105) and a drain electrode (106) spaced apart from the source electrode (105). The second conductive layer (150) includes a first layer (151) on the semiconductor layer (103) and a second layer (152) positioned on the first layer (151). The first layer (151) can be made of metal oxide. The second layer (152) can be made of aluminum or aluminum alloy.

Claims

1-14. -14. (canceled)

15. A TFT substrate comprising:

a substrate;

a semiconductor layer formed on the substrate, the semiconductor layer having a top surface and a bottom surface opposite to and facing away from the top surface;

a first conductive layer formed on the bottom surface of the semiconductor layer, the first conductive layer defining a gate electrode; and

a second conductive layer formed on the top surface of the semiconductor layer opposite to the first conductive layer, the second conductive layer defining a source electrode and a drain electrode spaced apart from the source electrode;

wherein the second conductive layer comprises a first layer positioned on the semiconductor layer, a second layer positioned on the first layer, and a third layer positioned on the second layer;

the second layer is made of aluminum or aluminum alloy;

both the third layer and the first layer are made of a same metal oxide;

an etching rate of the third layer is greater than an etching rate of the first layer when the second conductive layer is etched by a single etching solution or a single etching gas.

16. The TFT substrate of claim 15, wherein both the third layer and the first layer are made of a same metal oxide containing zinc;

the third layer has an atomic percentage of zinc larger than that of the first layer.

17. The TFT substrate of claim 15, wherein a groove is defined between the source electrode and the drain electrode;

the groove extends through the first layer, the second layer, and the third layer; and

wherein the size of the groove gradually decreases along a direction from the third layer to the first layer.

18. The TFT substrate of claim 15, further comprising a gate insulator layer, wherein a gate insulating layer is formed on the substrate and covers the gate electrode;

and the semiconductor layer is formed on the gate insulating layer.

19. The TFT substrate of claim 15, further comprising a passivation layer covering the semiconductor layer and the second conductive layer.

20. The TFT substrate of claim 15, further comprising a pixel electrode on the passivation layer, wherein the pixel electrode is electrically coupled to the drain electrode.

21. A method for making a TFT substrate comprising:

forming a gate electrode on a substrate;

forming a gate insulating layer on the substrate and covering the gate electrode;

forming a semiconductor layer on the gate insulating layer;

forming a first layer on the semiconductor layer, the first layer being made of a metal oxide;

forming a second layer on the first layer, the second layer being made of aluminum or aluminum alloy;

forming a third layer on the second layer, the third layer being made of a same metal oxide with the first layer; and

etching the first layer, the second layer, and the third layer to form a source electrode and a drain electrode spaced apart from the source electrode;

wherein an etching rate of the third layer is greater than an etching rate of the first layer.

22. The method of claim 21, wherein a groove is formed between the source electrode and the drain electrode;

the groove extends through the first layer, the second layer, and the third layer; and

wherein the size of the groove gradually decreases along a direction from the third layer to the first layer.

23. The method of claim 21, wherein both the third layer and the first layer are made of a same metal oxide containing zinc;

and the third layer has an atomic percentage of zinc larger than that of the first layer.

24. The method of claim 21, further comprising a step of forming a passivation layer covering the semiconductor layer and the third layer.