DISPLAY DEVICE AND GATE DRIVING CIRCUIT THEREOF, CONTROL METHOD AND VIRTUAL REALITY DEVICE

• US 20190005884A1
• Filed: 12/29/2017
• Published: 01/03/2019
• Est. Priority Date: 06/30/2017
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: YOO, Ooksang
• Granted Patent: US 10,504,442 B2
• Time in Patent Office: Days
• CPC Class Codes: G02B 27/0172 characterised by optical features
• CPC Class Codes: G06F 3/011 Arrangements for interaction with the human body, e.g. for user immersion in virtual reality blind teaching G09B21/00
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2310/0205 Simultaneous scanning of several lines in flat panels
• CPC Class Codes: G09G 2310/0264 Details of driving circuits
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/0261 in the context of movement of objects on the screen or movement of the observer relative to the screen
• CPC Class Codes: G09G 2320/045 Compensation of drifts in the characteristics of light emitting or modulating elements
• CPC Class Codes: G09G 2340/0414 Vertical resolution change
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3258 with pixel circuitry controlling the voltage across the light-emitting element
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals

Abstract

A display device and a gate driving circuit are disclosed. The display device includes a display panel comprising a plurality of data lines, a plurality of gate lines and a plurality of pixels arranged in a matrix in which the plurality of data lines and the plurality of gate lines intersect with each other; a system controller that sends image data of an input image to a display driver; and the display driver that drives the display panel by decreasing the number of shifts in gate signals applied to gate lines in a second area as compared with a first area. The first area is an area in which the input image is to be displayed in a first resolution in the display panel, and the second area is an area in which the input image is to be displayed in a second resolution smaller than the first resolution in the display panel.

Claims

1. A display device comprising:

a display panel including a plurality of data lines, a plurality of gate lines and a plurality of pixels arranged in a matrix form where the plurality of data lines and the plurality of gate lines intersect with each other; and

a system controller sending image data of an input image to a display driver, wherein the display driver drives the display panel by decreasing the number of shifts in gate signals applied to the plurality of gate lines in a second area where the input image is displayed with a second resolution lower than a first area where the input image is displayed in a first resolution in the display panel.

2. The display device according to claim 1, wherein the display driver further drives the display panel by decreasing the number of shifts in gate signals applied to the plurality of gate lines in a third area where the image data is displayed in a third resolution than the second resolution in the display panel.

3. The display device according to claim 2, wherein the system controller or the display driver determines the first area based on a user'"'"'s gaze, the second area around the first area, and respectively adjusts a resolution of the input image displayed in each of the first area and the second area to be the first resolution and the second resolution.

4. The display device according to claim 3, wherein the system controller or the display driver determines the third area other than the first area and the second area in the display panel, and adjusts a resolution of the input image displayed in the third area to be the third resolution.

5. The display device according to claim 1, wherein the display driver further comprises:

a data driver converts the image data of the input image into data voltages and outputting the data voltages to the plurality of data lines;

a gate driver outputting the gate signals synchronized with the data voltages to the plurality of gate lines; and

a timing controller controlling operation timings of the data driver and the gate driver based on a timing signal synchronized with the image data of the input image from the system controller.

6. The display device according to claim 5, wherein the timing controller controls the gate driver so that the gate driver adjusts the number of shifts in the gate signals in the first area and the second area in proportion to the first resolution and the second resolution.

7. The display device according to claim 5, wherein the gate driver reduces the number of shifts in the gate signals in the second area by simultaneously applying the gate signals to the plurality of gate lines in the second area a greater number of gate lines than the first area.

8. The display device according to claim 7, wherein the data driver writes the same image data to a plurality of pixel lines connected with the greater number of gate lines.

9. The display device according to claim 5, wherein the display driver further comprises:

a first image processor distinguishing the first area from the second area and determining a driving frame rate of the display panel, and controlling the gate driver based on the driving frame rate; and

a second image processor adjusting the input image in the first area to have the first resolution and the input mage in the second area to have the second resolution, and sending the image data with the resolution adjusted to the data driver.

10. The display device according to claim 9, wherein the second image processor processes a boundary between the first area and the second area by making a resolution of an image at the boundary alternate between the first resolution and the second resolution, or by shifting the boundary between the first area and the second area in a time axis.

11. The display device according to claim 9, wherein the first image processor and the second image processor are included in the timing controller.

12. The display device according to claim 1, wherein sizes of the first area and the second area are predetermined fixed values, or are varied based on one or more of the input image'"'"'s movement, a user'"'"'s head movement and the input image'"'"'s contents.

18. A virtual reality device including a display device according to claim 1.

19. The virtual reality device according to claim 18, wherein the display panel includes a left-eye display panel and a right-eye display panel.

20. The virtual reality device according to claim 19, wherein the left-eye display panel and the right-eye display panel shares the timing controller in the display driver.

13. A gate driving circuit for a display device, a display panel of the display device comprising a first area where an input image is displayed in a first resolution and a second area where the input image is displayed in a second resolution smaller than the first resolution, wherein the gate driving circuit comprising:

a shift register shifting pulses of gate signals and sequentially supplying the gate signals to a plurality of gate lines, the shift register including a plurality of stages connected as a cascade through a carry signal wiring; and

a multiplexer switching a path of an output signal of each of the plurality of stages,

wherein in the first area, the multiplexer provides the output signal of a previous stage to start terminals of a first number of next stages as an carry signal, and in the second area, the multiplexer provides the output signal of a previous stage to start terminals of a second number of next stages as a carry signal,

wherein the first number corresponds to the first resolution, and the second number corresponds to the second resolution.

14. The gate driving circuit according to claim 13, wherein the display panel further comprises a third area where the input image is displayed in a third resolution lower than the second resolution.

15. The gate driving circuit according to claim 14, wherein, in the third area, the multiplexer provides the output signal of a previous stage to start terminals of a third number of next stages as the carry signal, wherein the third number corresponds to the third resolution.

16. The gate driving circuit according to claim 14, wherein each of the plurality of stages comprises:

an output node connected to the plurality of gate lines on the display panel and outputting the output signal;

a Q node and a QB node;

a pulling-up transistor pulling up the output signal by charging the output node in response to a voltage at the Q node;

a pulling-down transistor pulling down the output signal by discharging the output node in response to a voltage at the QB node; and

a switching circuit charging the Q node in response to a start pulse or the carry signal input from the start terminal.

17. A method for controlling a gate driving circuit for a display device, a display panel of the display device including a first area where an input image is displayed in a first resolution and a second area where the input image is displayed in a second resolution lower than the first resolution, wherein the gate driving circuit including a shift register shifting pulses of gate signals and sequentially supplying the gate signals to a plurality of gate lines, the shift register including a plurality of stages connected as a cascade through a carry signal wiring;

and a multiplexer switching a path of an output signal of each of the plurality of stages, wherein the method comprises;

controlling the multiplexer to provide, in the first area, the output signal of a previous stage to start terminals of a first number of next stages as a carry signal; and

controlling the multiplexer to provide, in the second area, the output signal of a previous stage to start terminals of a second number of next stages as the carry signal, the first number corresponding to the first resolution, and the second number corresponding to the second resolution.