MICROCONTROLLER PROGRAMMABLE SYSTEM ON A CHIP

• US 20190012287A1
• Filed: 06/01/2018
• Published: 01/10/2019
• Est. Priority Date: 10/26/2000
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Snyder, Warren S., Mar, Monte
• Granted Patent: US 10,725,954 B2
• Time in Patent Office: Days
• CPC Class Codes: G05B 19/0423 Input/output
• CPC Class Codes: G05B 2219/25033 structure, control, syncronization, data, alarm, connect I-O line to interface
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 13/40 Bus structure for computer networks G06F15/163; for optical bus networks H04B10/25
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 15/7817 Specially adapted for signal processing, e.g. Harvard architectures
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files
• CPC Class Codes: G06G 7/06 Programming arrangements, e.g. plugboard for interconnecting functional units of the computer; Digital programming hybrid computers G06J
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: H03B 5/32 being a piezoelectric resonator selection of piezoelectric material H10N30/00
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03H 19/004 Switched capacitor networks
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/014 Modifications of generator to ensure starting of oscillations
• CPC Class Codes: H03K 3/02315 Stabilisation of output, e.g. using crystal

Abstract

Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

Claims

1-20. -20. (canceled)

21. A configurable analog processing circuit, comprising:

a programmable interconnect configurable to enable routing between a first and second signal paths;

a plurality of analog circuit blocks formed in a same integrated circuit comprising inputs and outputs coupled to the signal paths, each analog block providing at least one analog function, wherein the programmable interconnect comprises a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the same integrated circuit, and wherein at least two interconnected analog circuit blocks in combination provide at least another analog function;

a plurality of digital circuit blocks formed in the same integrated circuit comprising inputs and outputs coupled to the first and second signal paths; and

an internal input/output (I/O) bus comprising bus lines coupled to the first and second signal paths.

22. The configurable analog processing circuit of claim 21, wherein the programmable interconnect is configurable to connect multiple analog blocks with one another in series.

23. The configurable analog processing circuit of claim 21, wherein each analog circuit block is programmable between at least one of a plurality of different analog functions.

24. The configurable analog processing circuit of claim 21, wherein:

the same integrated circuit comprises at least one port as a signal connection point; and

the programmable interconnect is configurable to connect the at least one port to any of the analog circuit blocks.

25. The configurable analog processing circuit of claim 24, wherein the programmable interconnect is configurable to provide an analog signal input path from the at least one port to any of the analog circuit blocks.

26. The configurable analog processing circuit of claim 24, wherein the programmable interconnect is configurable to provide an analog signal output path from any of the analog circuit blocks to the at least one port.

27. The configurable analog processing circuit of claim 21, wherein at least one of the plurality of analog circuit blocks is coupled to at least one of the plurality of digital circuit blocks through the programmable interconnect to provide at least one mixed-signal function.

28. The configurable analog processing circuit of claim 21, wherein at least one of the plurality of analog circuit blocks is configurable to perform a first function in a first configuration and a second function in a second configuration.

29. The configurable analog processing circuit of claim 21, wherein the programmable interconnect has a first analog portion and a second digital portion.

30. A method comprising:

coupling an internal input/output (I/O) bus to a programmable interconnect;

coupling at least one of a plurality of programmable analog blocks to the programmable interconnect;

performing a first operation on a first signal received at the internal I/O bus with the at least one of the plurality of programmable analog blocks; and

performing at least a second operation on a second signal received at the internal I/O bus with at least two of the plurality of programmable analog blocks.

31. The method of claim 30, wherein the at least two of the plurality of programmable analog blocks comprises the at least one of the plurality of programmable analog blocks.

32. The method of claim 30, wherein performing the at least the second operation comprises performing a first sub-operation with a second analog block of the plurality of programmable analog blocks and performing a second sub-operation with a third analog block of the plurality of programmable analog blocks.

33. The method of claim 32, where the at least one of the plurality of programmable analog blocks is the same as either the second analog block rf the third analog block.

34. The method of claim 32, further comprising coupling the second analog block to the third analog block through an intra-block routing.

35. The method of claim 30, further comprising coupled at least one digital block of a plurality of programmable digital blocks to the programmable interconnect to perform at least one digital function.

36. The method of claim 30, further comprising coupling the internal I/O bus to a port for receiving signals.

37. A mixed-signal array comprising:

a programmable interconnect configurable to enable multiple signal routing first and second signal paths;

an array of analog circuit blocks formed in a same integrated circuit comprising inputs and outputs coupled to the signal paths, each analog block providing at least one analog function, wherein the programmable interconnect comprises a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the same integrated circuit, and wherein at least two interconnected analog circuit blocks provide at least another analog function;

an array of digital circuit blocks formed in the same integrated circuit comprising inputs and outputs coupled to the first and second paths; and

an internal input/output (I/O) bus comprising bus lines coupled to the first and second signal paths.

38. The mixed-signal array of claim 37, wherein the programmable interconnect is configurable to connect multiple analog blocks in series with one another.

39. The mixed-signal array of claim 37, wherein each analog circuit block is programmable between at least one of a plurality of different analog functions.

40. The mixed-signal array of claim 37, wherein at least one of the plurality of analog circuit blocks is coupled to at least one of the plurality of digital circuit blocks through the programmable interconnect to provide at least one mixed-signal function.

41. The mixed-signal array of claim 37, wherein at least one of the plurality of analog circuit blocks is configurable to perform a first function in a first configuration and a second function in a second configuration.