LOW VOLTAGE DROP CASCADED SYNCHRONOUS BOOTSTRAP SUPPLY CIRCUIT

• US 20190028094A1
• Filed: 07/18/2018
• Published: 01/24/2019
• Est. Priority Date: 07/20/2017
• Status: Active Grant

• Current Assignee: Efficient Power Conversion Corporation
• Original Assignee: Efficient Power Conversion Corporation
• Inventors: Reusch, David C., Biswas, Suvankar, de Rooij, Michael A.
• Granted Patent: US 10,637,456 B2
• Time in Patent Office: Days
• CPC Class Codes: G05F 1/46 wherein the variable actually regulated by the final control device is dc G05F1/625 takes precedence
• CPC Class Codes: H02M 1/088 for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A cascaded synchronous bootstrap supply circuit with reduced voltage drop between the cascaded bootstrap capacitors by replacing bootstrap diodes with gallium nitride (GaN) transistors. GaN transistors have a much lower forward voltage drop than diodes, thus providing a cascaded gate driver bootstrap supply circuit with a reduced drop in bootstrap capacitor voltage, which is particularly important as the number of levels increases.

Claims

1. A cascaded synchronous bootstrap gate driver circuit, comprising:

a plurality of drive control loops, each loop including a gallium nitride (GaN) transistor, a bootstrap capacitor, and a drive stage configured to selectively couple and decouple an adjacent drive control loop,

wherein each drive control loop is configured to selectively drive a power transistor of a multi-level converter.

2. The cascaded synchronous bootstrap gate driver circuit of claim 1, wherein each drive control loop further comprises a resistor.

3. The cascaded synchronous bootstrap gate driver circuit of claim 1, wherein each bootstrap capacitor is connected to a current terminal of a respective GaN transistor.

4. The cascaded synchronous bootstrap gate driver circuit of claim 1, wherein each GaN transistor is a depletion mode transistor.

5. The cascaded synchronous bootstrap gate driver circuit of claim 1, wherein each GaN transistor is an enhancement mode transistor.

6. The cascaded synchronous bootstrap gate driver circuit of claim 5, wherein each bootstrap capacitor comprises a first bootstrap capacitor, and each drive control loop further comprises a second bootstrap capacitor, wherein each first bootstrap capacitor is connected to a current terminal of a respective GaN transistor, and wherein each second bootstrap capacitor is connected to a gate terminal of a respective GaN transistor.

7. The cascaded synchronous bootstrap gate driver circuit of claim 1, wherein at least at one of the drive control loops further comprises a voltage regulator.

8. The cascaded synchronous bootstrap gate driver circuit of claim 7, wherein the voltage regulator comprises a linear dropout (LDO) regulator.

9. The cascaded synchronous bootstrap gate driver circuit of claim 7, wherein the voltage regulator comprises a switched-mode power supply.

10. The cascaded synchronous bootstrap gate driver circuit of claim 1, wherein each drive control loop further comprises a Zener diode in parallel with a respective bootstrap capacitor.

11. The cascaded synchronous bootstrap gate driver circuit of claim 1, comprising a base drive control loop that is a ground referenced loop, and wherein each of the other drive control loops is a non-ground referenced loop.

12. The cascaded synchronous bootstrap gate driver circuit of claim 11, wherein the base drive control loop comprises a bootstrap capacitor, a diode, a resistor, and a drive stage configured to selectively couple and decouple an adjacent drive control loop.

13. The cascaded synchronous bootstrap gate driver circuit of claim 1, wherein each drive control loop is configured to drive a separate power transistor in a sequence.

14. The cascaded synchronous bootstrap gate driver circuit of claim 1, wherein each drive stage comprises a controller, level shift logic, and complementary switches.

15. The cascaded synchronous bootstrap gate driver circuit of claim 1, comprising discrete components.

16. The cascaded synchronous bootstrap gate driver circuit of claim 1, comprising integrated circuit components.

17. The cascaded synchronous bootstrap gate driver circuit of claim 16, comprising a single integrated circuit.

18. The cascaded synchronous bootstrap gate driver circuit of claim 16, comprising multiple integrated circuits that are coupled together.

19. The cascaded synchronous bootstrap gate driver circuit of claim 1, further comprising a controller to balance voltage levels for flying capacitors of the multi-level converter.