MEMORY DEVICES HAVING SPECIAL MODE ACCESS
First Claim
1. A memory device comprising a register, a memory array, and a serial interface controller configured to receive and operate using a serial message to access the register that controls operation of the memory array by storing bits, the serial message having a format that comprises:
- a command field of the serial message configured to enable the serial interface controller to access the register;
a register address field of the serial message immediately following the command field indicating an address of the register; and
a data field of the serial message immediately following the register address field.
4 Assignments
0 Petitions
Accused Products
Abstract
Memory devices are provided that include special operating modes accessible upon receipt of a particular message from a host. One device includes a memory array, a special mode enable register, and a controller. When the controller receives a register write command to write first data into the special mode enable register and the memory device does so, the memory device operates in a first mode. When the controller receives a register write command to write second data into the special mode enable register and the memory device does so, the memory device operates in a second mode.
3 Citations
20 Claims
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1. A memory device comprising a register, a memory array, and a serial interface controller configured to receive and operate using a serial message to access the register that controls operation of the memory array by storing bits, the serial message having a format that comprises:
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a command field of the serial message configured to enable the serial interface controller to access the register; a register address field of the serial message immediately following the command field indicating an address of the register; and a data field of the serial message immediately following the register address field. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A system comprising:
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a master device configured to generate a clock signal; and a memory device configured to interface with the master device using a serial peripheral interface protocol, wherein the memory device comprises a controller; wherein the master device is configured to; enable the controller; send the clock signal to the controller; send a message to the controller, wherein the message comprises; a command field of the message configured to enable the controller to access volatile memory registers of the memory device; a register address field of the message immediately following the command field indicating an address of a volatile memory register of the volatile memory registers; and a data field of the message immediately following the register address field; wherein the controller is configured to access the volatile memory registers of the memory device that control operation of a memory array by storing bits in response to receiving the message from the master device. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
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15. A memory device, comprising:
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a serial interface controller; a register coupled to the serial interface controller; and a memory array coupled to the serial interface controller, wherein the serial interface controller is configured to receive and operate using a serial message comprising a command field configured to enable the serial interface controller to access the register, a register address field immediately following the command field indicating an address of the register, and a data field immediately following the register address field to access the register that controls operation of the memory array by storing bits. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification