CYCLE CONTROL CIRCUITS

• US 20190057730A1
• Filed: 01/05/2018
• Published: 02/21/2019
• Est. Priority Date: 08/21/2017
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: KIM, Chang Hyun
• Granted Patent: US 10,699,762 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 13/4217 with synchronous protocol
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A cycle control circuit may include a judgement pulse generation circuit, a detection signal generation circuit or a flag generation circuit. The judgement pulse generation circuit may be configured to set a predetermined value based on an initialization signal and a period signal, and to generate a judgment pulse. The detection signal generation circuit may be configured to generate a detection signal from a reference flag. The flag generation circuit may be configured to generate a reference flag based on a reference signal. A cycle of the reference signal may be maintained or adjusted based on the reference flag.

Claims

1. A cycle control circuit comprising:

a judgement pulse generation circuit configured to set a predetermined value in response to an initialization signal and configured to generate a judgement pulse in synchronization with a point of time that a time period corresponding to the predetermined value in units of a cycle of a clock signal elapses;

a detection signal generation circuit configured to generate a detection signal from a reference flag in response to the judgement pulse; and

a code generation circuit configured to generate a calibration code for controlling a cycle of a reference signal in response to the detection signal and the judgement pulse.

2. The cycle control circuit of claim 1, wherein the initialization signal is generated from an information signal during a mode register write operation.

3. The cycle control circuit of claim 1,

wherein the information signal includes mode information;

and

wherein the information signal is inputted to the cycle control circuit through a line that transmits an address or a command.

4. The cycle control circuit of claim 1, wherein the judgement pulse generation circuit is configured to initialize a count signal in response to a set control signal and a reset control signal which are generated from the initialization signal while a period signal is disabled and is configured to generate the judgement pulse by counting the count signal in response to a clock pulse which is generated from the clock signal while the period signal is enabled.

5. The cycle control circuit of claim 4,

wherein the count signal is initialized by the set control signal and the reset control signal to have an initial logic level combination;

and

wherein the count signal is sequentially counted from the initial logic level combination to a target logic level combination in response to the clock pulse.

6. The cycle control circuit of claim 1, wherein the judgement pulse generation circuit includes a counter control circuit which is configured to generate a set control signal and a reset control signal in response to the initialization signal and a period signal.

7. The cycle control circuit of claim 6, wherein the judgement pulse generation circuit is configured to buffer the initialization signal to generate the set control signal and the reset control signal while the period signal is disabled and is configured to generate the set control signal and the reset control signal having predetermined logic level combinations while the period signal is enabled.

8. The cycle control circuit of claim 6, wherein the judgement pulse generation circuit further includes a count signal generation circuit which is configured to initialize all of bits included in a count signal in response to the set control signal and the reset control signal and is configured to output the count signal that is counted in response to a clock pulse.

9. The cycle control circuit of claim 8, wherein the judgement pulse generation circuit further includes a count signal detection circuit which is configured to generate the judgement pulse if the count signal has a predetermined target logic level combination.

10. The cycle control circuit of claim 9, wherein the count signal detection circuit includes:

an initial judgement signal generation circuit configured to generate an initial judgement signal in response to a set signal and a reset signal, wherein the set signal is generated in response to the clock pulse and the count signal, and the reset signal is generated in response to the period signal; and

a judgement pulse output circuit configured to generate the judgement pulse from the initial judgement signal.

11. The cycle control circuit of claim 1, wherein the detection signal generation circuit is configured to latch the reference flag in synchronization with a point of time that the judgement pulse is generated and is configured to generate the detection signal from the latched reference flag.

12. The cycle control circuit of claim 1, wherein the code generation circuit is synchronized with a point of time that the judgement pulse is generated to generate the calibration code if the detection signal has a first logic level and to output the calibration code as a sense code if the detection signal has a second logic level.

13. The cycle control circuit of claim 1, wherein the code generation circuit includes:

an update pulse generation circuit configured to generate a first update pulse and a second update pulse in response to the judgement pulse and the detection signal;

a first code output circuit configured to output the calibration code that is counted in synchronization with the first update pulse; and

a second code output circuit configured to output the calibration code as a sense code in synchronization with the second update pulse.

14. A cycle control circuit comprising:

a judgement pulse generation circuit configured to set a predetermined value in response to an initialization signal and configured to generate a judgement pulse in synchronization with a point of time that a time period corresponding to the predetermined value in units of a cycle of a clock signal elapses;

a flag generation circuit configured to generate a reference flag in response to a period signal and a reference signal, the reference signal having a cycle that is controlled by a calibration code; and

a code generation circuit configured to generate the calibration code and a sense code in response to the judgement pulse and a detection signal generated from the reference flag.

15. The cycle control circuit of claim 14, wherein the initialization signal is generated from an information signal during a mode register write operation.

16. The cycle control circuit of claim 14, wherein the judgement pulse generation circuit is configured to initialize a count signal to have an initial logic level combination in response to a set control signal and a reset control signal which are generated from the initialization signal while the period signal is disabled and is configured to generate the judgement pulse by sequentially counting the count signal from the initial logic level combination to a target logic level combination in response to a clock pulse which is generated from the clock signal while the period signal is enabled.

17. The cycle control circuit of claim 14, wherein the judgement pulse generation circuit includes:

a counter control circuit configured to generate a set control signal and a reset control signal in response to the initialization signal and the period signal;

a count signal generation circuit configured to initialize all of bits included in a count signal in response to the set control signal and the reset control signal and configured to output the count signal that is counted in response to a clock pulse; and

a count signal detection circuit configured to generate the judgement pulse if the count signal has a target logic level combination.

18. The cycle control circuit of claim 14, wherein the flag generation circuit generates the reference flag in synchronization with a point of time that a time period corresponding to a predetermined number of cycles of the reference signal elapses after the period signal is enabled.

19. The cycle control circuit of claim 18, wherein the flag generation circuit includes:

a fuse set signal generation circuit configured to generate the fuse set signal in synchronization with the point of time that the time period corresponding to the predetermined number of cycles of the reference signal elapses after the period signal is enabled; and

a flag latch configured to generate the reference flag in response to the fuse set signal and a fuse reset signal.

20. The cycle control circuit of claim 14, further comprising a detection signal generation circuit configured to latch the reference flag in synchronization with a point of time that the judgement pulse is generated and configured to generate the detection signal from the latched reference flag.

21. The cycle control circuit of claim 14, wherein the code generation circuit is synchronized with a point of time that the judgement pulse is generated to generate the calibration code if the detection signal has a first logic level and to output the calibration code as a sense code if the detection signal has a second logic level.

22. The cycle control circuit of claim 14, wherein the code generation circuit includes:

an update pulse generation circuit configured to generate a first update pulse and a second update pulse in response to the judgement pulse and the detection signal;

a first code output circuit configured to output the calibration code that is counted in synchronization with the first update pulse; and

a second code output circuit configured to output the calibration code as a sense code in synchronization with the second update pulse.

23. A cycle control circuit comprising:

a judgement pulse generation circuit configured to set a predetermined value based on an initialization signal and a period signal, and configured to generate a judgement pulse in synchronization with a point of time that a time period corresponding to the predetermined value in units of a cycle of a clock signal elapses; and

a flag generation circuit configured to generate a reference flag based on the period signal and a reference signal,

wherein a cycle of the reference signal is maintained at a constant value after an operation for adjusting the cycle of the reference signal terminates based on the reference flag.

24. The cycle control circuit of claim 23, further comprising:

a code generation circuit configured to increase or decrease the cycle of the reference signal in response to the judgement pulse and a detection signal generated from the reference flag.

25. The cycle control circuit of claim 24, wherein the code generation circuit is configured to maintain the cycle of the reference signal and output information on the cycle of the reference signal in response to the enablement of the detection signal generated from the reference flag.

26. A cycle control circuit comprising:

a judgement pulse generation circuit configured to set a predetermined value based on an initialization signal and a period signal, and configured to generate a judgement pulse in synchronization with a point of time that a time period corresponding to the predetermined value in units of a cycle of a clock signal elapses; and

a detection signal generation circuit configured to generate a detection signal from a reference flag in response to the judgement pulse, the reference flag generated based on a reference signal and the period signal,

wherein a cycle of the reference signal is maintained at a constant value after an operation for adjusting the cycle of the reference signal terminates based on the reference flag.

27. The cycle control circuit of claim 26, further comprising:

a code generation circuit configured to increase or decrease the cycle of the reference signal in response to the judgement pulse and the detection signal.

28. The cycle control circuit of claim 27, wherein the code generation circuit is configured to maintain the cycle of the reference signal and output information on the cycle of the reference signal in response to the enablement of the detection signal.

29. The cycle control circuit of claim 26, further comprising:

a flag generation circuit configured to generate the reference flag signal in synchronization with a point of time that a time period corresponding to a predetermined number of cycles of the reference signal elapses after the period signal is enabled.