Memory Device Comprising An Electrically Floating Body Transistor

• US 20190066768A1
• Filed: 10/25/2018
• Published: 02/28/2019
• Est. Priority Date: 01/15/2014
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Han, Jin-Woo, Widjaja, Yuniarto
• Granted Patent: US 10,522,213 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 15/04 using semiconductor elements
• CPC Class Codes: G11C 15/043 using capacitive charge storage elements
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A memory cell comprising includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region.

Claims

1-20. -20. (canceled)

21. A semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells each include:

an electrically floating body region comprising a first conductivity type selected from p-type conductivity type and n-type conductivity type;

a source line region comprising a second conductivity type selected from said p-type conductivity type and said n-type conductivity type and being different from said first conductivity type, said source line region in physical contact with said floating body transistor;

a drain region comprising said second conductivity type in physical contact with said floating body region and spaced apart from said source line region; and

a charge injector region, wherein said charge injection region comprises said second conductivity type and is in physical contact with said floating body region and spaced apart from said source line region and said drain region;

a gate region positioned in between said source line region and said drain region, the gate region being positioned between said source line region and said charge injector region, and the gate region being positioned between said drain region and said charge injector region;

wherein said floating body region is configured to have more than one stable state through an application of a bias on said charge injector region; and

wherein said charge injector region is commonly connected to at least two of said semiconductor memory cells.

22. The semiconductor memory array of claim 21 configured such that a holding operation on said memory cells does not require any interruption to access to said memory cells.

23. The semiconductor memory array of claim 21, wherein said charge injector region is configured to perform a holding operation on all of said memory cells connected to said charge injector region.

24. The semiconductor memory array of claim 21, wherein application of a bias to said charge injector region in performance of a holding operation also increases a size of a memory window of said floating body region.

25. The semiconductor memory array of claim 21, wherein a depth of said charge injector region is less than a depth of said drain region or said source line region.

26. The semiconductor memory array of claim 21, wherein a depth of said charge injector region is less than a depth of said floating body region.

27. The semiconductor memory array of claim 21 fabricated in a silicon-on-insulator (SOI) substrate.

28. The semiconductor memory array of claim 21 fabricated in a bulk silicon substrate and further comprising a buried well region comprising said second conductivity type.

29. The semiconductor memory array of claim 21 formed in a fin structure fabricated in a bulk silicon substrate.

30. The semiconductor memory array of claim 21 formed in a fin structure fabricated in a silicon-on-insulator (SOI) substrate.

31. A semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each of said memory cells is connected in series with an access device, and wherein each said memory cell includes:

an electrically floating body region comprising a first conductivity type selected from p-type conductivity type and n-type conductivity type;

a source line region comprising a second conductivity type selected from said p-type conductivity type and said n-type conductivity type and being different from said first conductivity type, said source line region in physical contact with said floating body transistor;

a drain region comprising said second conductivity type in physical contact with said floating body region and spaced apart from said source line region; and

a charge injector region, wherein said charge injection region comprises said second conductivity type and is in physical contact with said floating body region and spaced apart from said source line region and said drain region;

a gate region positioned in between said source line region and said drain region, the gate region being positioned between said source line region and said charge injector region, and the gate region being positioned between said drain region and said charge injector region;

wherein said floating body region is configured to have more than one stable state through an application of a bias on said charge injector region; and

wherein said charge injector region is commonly connected to at least two of said semiconductor memory cells.

32. The semiconductor memory array of claim 31 configured such that a holding operation on said memory cells does not require any interruption to access to said memory cells.

33. The semiconductor memory array of claim 31, wherein said charge injector region is configured to perform a holding operation on all of said memory cells connected to said charge injector region.

34. The semiconductor memory array of claim 31, wherein application of a bias to said charge injector region in performance of a holding operation also increases a size of a memory window of said floating body region.

35. The semiconductor memory array of claim 31, wherein a depth of said charge injector region is less than a depth of said drain region or said source line region.

36. The semiconductor memory array of claim 31, wherein a depth of said charge injector region is less than a depth of said floating body region.

37. The semiconductor memory array of claim 31 fabricated in a silicon-on-insulator (SOI) substrate.

38. The semiconductor memory array of claim 31 fabricated in a bulk silicon substrate and further comprising a buried well region comprising said second conductivity type.

39. The semiconductor memory array of claim 31 formed in a fin structure fabricated in a bulk silicon substrate.

40. The semiconductor memory array of claim 31 formed in a fin structure fabricated in a silicon-on-insulator (SOI) substrate.