METHODS FOR DEPOSITING A DOPED GERMANIUM TIN SEMICONDUCTOR AND RELATED SEMICONDUCTOR DEVICE STRUCTURES

• US 20190067004A1
• Filed: 08/22/2017
• Published: 02/28/2019
• Est. Priority Date: 08/22/2017
• Status: Active Grant

• Current Assignee: ASM IP Holding B.V. (ASM International NV)
• Original Assignee: ASM IP Holding B.V. (ASM International NV)
• Inventors: Kohen, David, Profijt, Harald Benjamin
• Granted Patent: US 10,236,177 B1
• Time in Patent Office: Days
• CPC Class Codes: C23C 16/06 characterised by the deposition of metallic material
• CPC Class Codes: C23C 16/56 After-treatment
• CPC Class Codes: C30B 25/02 Epitaxial-layer growth
• CPC Class Codes: C30B 29/52 Alloys
• CPC Class Codes: C30B 33/02 Heat treatment C30B33/04, C30B33/06 take precedence
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02535 including tin
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66803 : with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7851 : with the body tied to the substrate

Abstract

A method for depositing a germanium tin (Ge_1-xSn_x) semiconductor is disclosed. The method may include; providing a substrate within a reaction chamber, heating the substrate to a deposition temperature and exposing the substrate to a germanium precursor and a tin precursor. The method may further include; depositing a germanium tin (Ge_1-xSn_x) semiconductor on the surface of the substrate, and exposing the germanium tin (Ge_1-xSn_x) semiconductor to a boron dopant precursor. Semiconductor device structures including a germanium tin (Ge_1-xSn_x) semiconductor formed by the methods of the disclosure are also provided.

Claims

1. A method of depositing a doped germanium tin (Ge_1-xSn_x) semiconductor comprising:

providing a substrate within a reaction chamber;

heating the substrate to a deposition temperature;

exposing the substrate to a germanium precursor and a tin precursor in the reaction chamber;

depositing a germanium tin (Ge_1-xSn_x) semiconductor on a surface of the substrate;

removing the germanium precursor and the tin precursor from the reaction chamber;

after the step of depositing, exposing the germanium tin (Ge_1-xSn_x) semiconductor to a boron dopant precursor while no tin precursor and no germanium precursor are introduced to the reaction chamber; and

after the step of exposing, annealing the germanium tin (Ge_1-xSn_x) semiconductor.

2. The method of claim 1, further comprising a pre-deposition bake.

3. The method of claim 1, wherein exposing the substrate to the germanium precursor and the tin precursor further comprises exposing the substrate to an initial boron dopant precursor.

4. The method of claim 1, wherein heating the substrate to the deposition temperature further comprises heating the substrate to a deposition temperature of between approximately 275°

C. and approximately 400°

C.

5. The method of claim 1, further comprising selecting the germanium precursor to comprise at least one of:

germane (GeH₄), digermane (Ge₂H₆), trigermane (Ge₃H₈), or germylsilane (GeH₆Si).

6. The method of claim 1, further comprising selecting the tin precursor to comprise at least one of tin tetrachloride (SnCl₄) or tin deuteride (SnD₄).

7. The method of claim 1, further comprising selecting the boron dopant precursor to comprise at least one of diborane (B₂H₆) or boron trichloride (BCl₃).

8. The method of claim 1, wherein exposing the substrate to the germanium precursor and the tin precursor further comprises co-flowing the germanium precursor and the tin precursor into the reaction chamber.

9. The method of claim 1, wherein depositing the germanium tin (Ge_1-xSn_x) semiconductor on the surface of the substrate further comprises depositing the germanium tin (Ge_1-xSn_x) semiconductor to a thickness of between approximately 1 nanometer to approximately 15 nanometers.

10. The method of claim 1, wherein exposing the germanium tin (Ge_1-xSn_x) semiconductor to the boron dopant precursor further comprises exposing the germanium tin (Ge_1-xSn_x) semiconductor to the boron dopant precursor for a time period of between approximately 1 second and approximately 60 seconds.

11. The method of claim 1, wherein a deposition cycle comprises:

exposing the substrate to the germanium precursor and the tin precursor, depositing the germanium tin (Ge_1-xSn_x) semiconductor, and exposing the germanium tin (Ge_1-xSn_x) semiconductor to the boron dopant precursor.

12. The method of claim 11, further comprising performing two or more deposition cycles prior to the step of annealing.

13. The method of claim 12, wherein performing two or more deposition cycles further comprises depositing the germanium tin (Ge_1-xSn_x) semiconductor to a thickness of between approximately 40 nanometers and approximately 60 nanometers.

14. The method of claim 1, wherein exposing the germanium tin (Ge_1-xSn_x) semiconductor to the boron dopant precursor further comprises doping the germanium tin (Ge_1-xSn_x) semiconductor to a dopant concentration of greater than 1×

10²¹ dopants per cubic centimeter.

15. The method of claim 12, wherein the step of annealing the germanium tin (Ge_1-xSn_x) semiconductor is performed at a temperature between approximately 350°

C. and approximately 650°

C. after performing two or more deposition cycles.

16. The method of claim 1, wherein depositing the germanium tin (Ge_1-xSn_x) semiconductor on the surface of the substrate further comprises depositing the germanium tin (Ge_1-xSn_x) with a tin (Sn) content of greater than approximately x=0.05.

17. A semiconductor device structure comprising the germanium tin (Ge_1-xSn_x) semiconductor deposited by the method of claim 1.

18. The semiconductor device structure of claim 17, wherein the germanium tin (Ge_1-xSn_x) semiconductor comprises at least one of a source or a drain region of a transistor structure.

19. The semiconductor device structure of claim 18, wherein the transistor structure comprises a PMOSFET.

20. The semiconductor device structure of claim 18, further comprising forming an electrical contact to the source or drain region of the transistor structure, wherein the electrical contact has an electrical resistivity of less than 1×

10<sup>−

9</sup> Ohm·

cm².