Display Device and Method of Manufacturing the Same

• US 20190079336A1
• Filed: 11/13/2018
• Published: 03/14/2019
• Est. Priority Date: 07/25/2014
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: NAM, Yousung, WOO, Changseung, HONG, Soonhwan
• Granted Patent: US 10,727,255 B2
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/13338 Input devices, e.g. touch panels
• CPC Class Codes: G02F 1/1337 Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
• CPC Class Codes: G02F 1/133723 Polyimide, polyamide-imide
• CPC Class Codes: G02F 1/133788 by light irradiation, e.g. linearly polarised light photo-polymerisation
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A display device optimized to operate in a low frame rate mode under certain predetermined conditions is provided. To reduce pixel discharge during the low frame rate mode, the display device employees the TFTs with metal oxide semiconductor layer, the optical alignment layer with an upper portion and a lower portion having different resistivity. In addition, a passivation layer is provided between the optical alignment layer and the pixel or the common electrode for compensating the low resistivity of the lower portion of the optical alignment layer. As such, various visual defects associated with the pixel discharge can be reduced even when the display device is operating under the low frame rate mode.

Claims

1. A method of manufacturing a display device, the method comprising:

forming a thin film transistor on a substrate, the thin film transistor comprising a semiconductor layer made of a metal oxide;

forming a first passivation layer on the thin film transistor;

forming an organic insulation layer on the first passivation layer in which an auxiliary wire is placed within the organic insulation layer;

forming a common electrode on the organic insulation layer;

forming a second passivation layer on the common electrode;

forming a pixel electrode on the second passivation layer;

forming a third passivation layer on the pixel electrode; and

forming a lower photo alignment layer on the third passivation layer.

2. The method of claim 1, wherein the forming of the organic insulation layer and the auxiliary wire comprises:

forming a lower organic insulation layer on the first passivation layer;

forming the auxiliary wire on the lower organic insulation layer; and

forming an upper organic insulation layer to cover the auxiliary wire on the lower organic insulation layer.

3. The method of claim 1, further comprising a step for forming a contact hole that exposes the auxiliary wire placed within the organic insulation layer such that the common electrode placed on the organic insulation layer is in contact with the auxiliary wire through the contact hole.

4. The method of claim 1, wherein the third passivation layer is formed in an atmosphere in which the ratio of silane gas and ammonia gas in the atmosphere ranges between 1:

10 and 1;

5.

5. The method of claim 1, further comprising:

forming an upper substrate facing the substrate and comprising a black matrix, color filters, and an upper photo alignment layer; and

sealing a liquid crystal layer between the substrate and the upper substrate.

6. The method of claim 5, wherein polymer chains in the upper and lower alignment layers contain a material that facilitates alignment of the polymer chains upon ultra violet (UV) light irradiation.

7. The method of claim 5, wherein the liquid crystal layer includes negative liquid crystals.

8. The method of claim 1, wherein the third passivation layer includes a higher resistivity than the lower photo alignment layer.

9. The method of claim 8, wherein the resistivity of the third passivation layer is 1×

10¹⁴ Ω

cm or greater.

10. The method of claim 1, wherein the third passivation layer comprises at least one of silicon oxide film (SiOx) and silicon nitride film (SiNx), and has a thickness of 500 to 4,000 Å

.

11. The method of claim 1, wherein the lower photo alignment layer comprising an upper part and a lower part, the upper part comprising a polymer material with a photodegradable material and of a first average molecular weight, the lower part comprising a polymer material without the photodegradable material and of a second average molecular weight lighter than the first average molecular weight.

12. The method of claim 11, wherein the polymer material comprises polyimide having a molecular weight of 100,000 DA or more.

13. The method of claim 1, wherein the thin film transistor is connected to a data line and a gate line, and the auxiliary wire extends along and at least partially overlaps the data line.

14. The method of claim 1, wherein a driver is configured to selectively adjust a timing of a signal supplied to the thin film transistor according to a driving mode.

15. The method of claim 14, wherein the driving mode includes a first frequency mode and a second frequency mode different from the first frequency mode, and wherein an image data on the display device is a moving image in the first frequency mode and an image data on the display device is a still image in the second frequency mode.