CIRCUIT AND METHOD FOR STORING INFORMATION IN NON-VOLATILE MEMORY DURING A LOSS OF POWER EVENT

• US 20190102261A1
• Filed: 09/29/2017
• Published: 04/04/2019
• Est. Priority Date: 09/29/2017
• Status: Active Grant

• Current Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Original Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Inventors: Cesaretti, Juan Manuel, Milesi, Alejandro Gabriel
• Granted Patent: US 10,430,296 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/1456 Hardware arrangements for backup
• CPC Class Codes: G06F 11/1469 Backup restoration techniques
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30
• CPC Class Codes: G11C 16/225 Preventing erasure, programming or reading when power supply voltages are outside the required ranges
• CPC Class Codes: G11C 5/005 Circuit means for protection against loss of information of semiconductor storage devices
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits

Abstract

A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit including an input for receiving a power loss signal in response to a power loss from at least one power source, an input configured to receive data from a volatile memory, a single block of non-volatile matrix of memory cells and a driver circuit coupled to said single row of non-volatile matrix of memory cells. The driver circuit is configured to write data to and read data from said single block of non-volatile matrix of memory cells. The single block of non-volatile matrix of memory cells can be provided as a single row electrically erasable programmable read only memory (EEPROM).

Claims

1. A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit comprising:

a nonvolatile matrix of memory cells having a plurality of blocks of memory cells;

an energy storage device;

one or more switch elements configured to selectively couple said energy storage device to independently power a single block of said plurality of blocks of memory cells in response to receiving a power loss signal; and

a driver circuit coupled to said single block of memory cells, said driver circuit configured to write data to and read data from said single block of memory cells, the driver circuit further configured to write data from said volatile memory to said single block using a single control pulse in response to receiving the power loss signal.

2. The data storage circuit of claim 1 wherein said single block of non-volatile matrix of memory cells is provided as a single block electrically erasable programmable read only memory (EEPROM).

3. The data storage circuit of claim 2 wherein said driver circuit is provided as a single block EEPROM driver circuit coupled to said single block EEPROM, said EEPROM driver circuit configured to write data to and read data from said single block EEPROM.

4. The data storage circuit of claim 3 wherein said single block of non-volatile matrix of memory cells is a single row EEPROM.

5. The data storage circuit of claim 3:

wherein said single block EEPROM is provided as one of a plurality of rows and a plurality of columns of a matrix of EEPROM cells configured to be written to by utilizing collective row and column operations by one or more driver circuits; and

wherein said single block EEPROM corresponds to an independent block of said matrix of EEPROM cells; and

wherein said single block of EEPROM cells is further configured such that in response to the data storage circuit receiving the power loss signal, data is written from the volatile memory to said single block of EEPROM cells; and

a controller configured to receive the power loss signal and in response thereto to write data from the volatile memory to said independent single block of non-volatile matrix of memory cells via said single block EEPROM driver circuit.

6. The data storage circuit of claim 1:

wherein said single block of non-volatile matrix of memory cells is provided as one of a plurality of rows and a plurality of columns of a non-volatile matrix of memory cells configured to be written to by utilizing collective row and column operations by one or more driver circuits; and

wherein said single block of non-volatile matrix of memory cells corresponds to an independent block of said matrix of memory cells; and

wherein said single block of non-volatile matrix of memory cells is further configured and arranged for being written to independently of the other memory cells of said matrix of memory cells in response to receiving the power loss signal; and

a controller configured to receive the power loss signal and in response thereto to write data from the volatile memory to said independent single block of non-volatile matrix of memory cells via said driver circuit.

7. A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit comprising:

a non-volatile matrix of memory cells comprising a plurality of rows and a plurality of columns configured to be written to by utilizing collective row and column operations in the absence of a power loss, the plurality of memory cells including an independent subset block of memory cells further configured to be powered and written to independently of each of the other memory cells in response to receiving a power loss signal; and

a controller configured to receive the power loss signal and to responsively write data from said volatile memory to said independent subset block.

8. The data storage circuit of claim 7 wherein the non-volatile matrix of memory cells forms the memory of an EEPROM, the data storage circuit further comprising:

a plurality of EEPROM column drivers and a plurality of EEPROM row drivers, the plurality of EEPROM column and row drivers arranged and configured to coordinate reading and writing to multiple rows and columns of the EEPROM; and

an energy storing device;

wherein the controller is configured, in response to the power loss signal, to selectively direct energy from the energy storing device to writing of data from said volatile memory to said independent subset block.

9. The data storage circuit of claim 8 further comprising a clock signal generator, wherein the coordinated reading and writing from said plurality of column and row drivers is timed to a clock signal from the clock signal generator and wherein the writing of data from said volatile memory to said independent subset block in response to the power loss signal is controlled without utilizing a clock signal.

10. The data storage circuit of claim 9 wherein the controller is configured to write to the independent subset block in response to a power loss signal without overwriting at least a portion of the plurality of memory cells of the EEPROM.

11. The data storage circuit of claim 10 wherein the controller is configured to write to the independent subset block in response to a power loss signal without writing to any other of the plurality of memory cells of the EEPROM.

12. The data storage circuit of claim 11 further comprising an independent memory driver configured to be selectively powered from the energy storing device to write to the independent subset block in response to a power loss signal.

13. The data storage circuit of claim 12 wherein said independent subset block is an independent row of said EEPROM further comprising an independent row driver configured to be selectively powered from the energy storing device to write to the independent row in response to a power loss signal.

14. The data storage circuit of claim 13 wherein the energy storing device comprises a charge pump and a charge pump switch configured to release power stored in the charge pump when switched, the charge pump switch coupled between the charge pump and the independent memory driver and configured to switch closed by receiving a signal from the controller in response to the power loss signal.

15. The data storage circuit of claim 8 wherein the controller is arranged and configured to write data from said volatile memory to said independent subset block in less than about 10 milliseconds.

16-17. -17. (canceled)

18. A method of transferring data from a volatile memory circuit to an EEPROM during a power interruption, the method comprising:

transmitting a power loss signal in a primary circuit, the power loss signal representing that a power supply coupled to the primary circuit has been interrupted; and

receiving the power loss signal in a controller, the controller configured to, in response to receiving the power loss signal, write data from the volatile memory circuit to an independent EEPROM memory block of a matrix of memory cells of the EEPROM, the matrix having a plurality of rows and a plurality of columns of memory cells, wherein the writing occurs while not powering any of the rows of the EEPROM that do not contain the independent memory block; and

operating the matrix of memory cells, including the independent memory block, utilizing collective row and column EEPROM operations while the power loss signal is not active.

19. The method of claim 18 wherein the writing to the independent block of the EEPROM is powered by residual power in the primary circuit.

20. The method of claim 19 wherein the residual power is supplied by power stored in a charge pump, the charge pump'"'"'s residual power released by switching a charge pump switch in response to the power loss signal.

21. The method of claim 18 wherein writing data from the volatile memory circuit to an independent EEPROM block is executed without utilizing a clock signal.

22. A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit comprising means for writing data, in response to a power loss in the data storage circuit, from the volatile memory to an independent memory block of a matrix of non-volatile memory cells while not to powering other memory cells of the matrix.

23. The data storage circuit of claim 22 wherein the non-volatile memory cells are cells of an EEPROM.

24. An integrated data storage circuit (IC) for storing data from volatile memory in response to a power loss, the IC comprising:

volatile memory means;

energy storage means;

non-volatile memory means;

means for detecting a loss of power to the IC and for providing a power loss signal in response to detection of a loss of power; and

means, responsive to the detection of the power loss signal, for transferring data from said volatile memory means to said non-volatile memory means by independently powering a portion of said non-volatile memory means from said energy storage means.

25. The IC of claim 24 wherein the non-volatile memory means is an EEPROM block means.

26. The IC of claim 24 wherein the energy storage means is capacitor and charge pump means.

27-29. -29. (canceled)