SOLID-STATE IMAGING SENSOR AND SOLID-STATE IMAGING DEVICE

• US 20190104268A1
• Filed: 10/02/2017
• Published: 04/04/2019
• Est. Priority Date: 10/02/2017
• Status: Active Grant

• Current Assignee: Sony Semiconductor Solutions Corporation (Sony Group Corp.)
• Original Assignee: Sony Semiconductor Solutions Corporation (Sony Group Corp.)
• Inventors: Shirini, Soraya, Ueno, Takahisa, Hanzawa, Katsuhiko
• Granted Patent: US 10,477,133 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14623 Optical shielding
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14641 Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 23/73 by influencing the exposure time
• CPC Class Codes: H04N 25/42 by switching between different modes of operation using different resolutions or aspect ratios, e.g. switching between interlaced and non-interlaced mode
• CPC Class Codes: H04N 25/583 with different integration times
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/709 Circuitry for control of the power supply
• CPC Class Codes: H04N 25/74 Circuitry for scanning or addressing the pixel array
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion

Abstract

There is provided a solid-state image sensor including: a selection signal terminal configured to receive a selection signal designated by a pixel address in a two-dimensionally arranged pixel array; a photoelectric conversion section configured to generate a charge in accordance with incident light and store the charge in accordance with the selection signal; and a charge retention section configured to retain the charge stored in the photoelectric conversion section at a prescribed timing.

Claims

1. A solid-state image sensor comprising:

a selection signal terminal configured to receive a selection signal designated by a pixel address in a two-dimensionally arranged pixel array;

a photoelectric conversion section configured to generate a charge in accordance with incident light and store the charge in accordance with the selection signal; and

a charge retention section configured to retain the charge stored in the photoelectric conversion section at a prescribed timing.

2. The solid-state image sensor according to claim 1, further comprising:

a charge release section configured to release the charge stored in the photoelectric conversion section in accordance with the selection signal.

3. The solid-state image sensor according to claim 2,

wherein the selection signal includes

a first decoded signal that shows a decoding result of a horizontal address in the pixel array and

a second decoded signal that shows a decoding result of a vertical address in the pixel array, and

the charge release section releases the charge stored in the photoelectric conversion section in a case where both of the first decoded signal and the second decoded signal are effective.

4. The solid-state image sensor according to claim 3,

wherein the charge release section includes

a first transistor in which a power source is connected to one end and that comes into conduction in a case where the first decoded signal is effective and

a second transistor that is connected in series between the first transistor and the photoelectric conversion section and that comes into conduction in a case where the second decoded signal is effective.

5. The solid-state image sensor according to claim 3,

wherein the charge release section includes

a first transistor in which one of the first decoded signal and the second decoded signal is connected to a gate and another of the first decoded signal and the second decoded signal is connected to a drain, the first transistor supplying an effective signal from a source in a case where both of the first decoded signal and the second decoded signal are effective, and

a second transistor that is connected in series between a power source and the photoelectric conversion section and that comes into conduction in a case where an effective signal is supplied from the source of the first transistor.

6. The solid-state image sensor according to claim 3,

wherein the charge release section includes

a transistor that is connected in series between a power source and the photoelectric conversion section, in which one of the first decoded signal and the second decoded signal is connected to a first gate and another of the first decoded signal and the second decoded signal is connected to a second gate, and that comes into conduction in a case where both of the first decoded signal and the second decoded signal are effective.

7. The solid-state image sensor according to claim 3, comprising:

a first chip including

the selection signal terminal,

the photoelectric conversion section, and

the charge retention section; and

a second chip including the charge release section and being stacked on the first chip.

8. The solid-state image sensor according to claim 1, further comprising:

a charge/voltage conversion section configured to store the charge retained in the charge retention section in order to convert the charge to a voltage; and

a first transfer transistor and a second transfer transistor connected in series to each other and configured to transfer the charge retained in the charge retention section to the charge/voltage conversion section,

wherein the charge retention section is formed integrally with a diffusion layer of the first transfer transistor.

9. The solid-state image sensor according to claim 1,

wherein the solid-state image sensor includes a plurality of pixels each including

the selection signal terminal,

the photoelectric conversion section, and

the charge retention section, and

the solid-state image sensor further includes a charge/voltage conversion section configured to store the charge retained in the charge retention section in each of the plurality of pixels in order to convert the charge to a voltage.

10. The solid-state image sensor according to claim 9, further comprising:

a charge resetting section configured to reset the charge stored in the charge/voltage conversion section.

11. The solid-state image sensor according to claim 9, further comprising:

a signal amplifying section configured to amplify the charge stored in the charge/voltage conversion section and output a pixel signal at a level in accordance with the charge.

12. A solid-state imaging device comprising:

a pixel array in which a plurality of pixels each configured to convert incident light to a pixel signal are two-dimensionally arranged;

an exposure control circuit configured to supply a selection signal that designates one of the plurality of pixels and control exposure in the designated pixel; and

a reading circuit configured to read the pixel signal from each of the plurality of pixels,

wherein each of the plurality of pixels includes

a selection signal terminal configured to receive the selection signal,

a photoelectric conversion section configured to generate and store a charge in accordance with the incident light,

a charge release section configured to release the charge stored in the photoelectric conversion section in accordance with the selection signal,

a charge retention section configured to retain the charge stored in the photoelectric conversion section at a prescribed timing, and

a charge/voltage conversion section configured to store the charge retained in the charge retention section in order to convert the charge to the pixel signal that is a voltage signal.

13. The solid-state imaging device according to claim 12,

wherein the exposure control circuit includes decoders each configured to decode each of positions in a horizontal direction and a vertical direction of a pixel address in the pixel array, and supplies the selection signal on a basis of a result of the decoding.

14. The solid-state imaging device according to claim 12,

wherein the exposure control circuit supplies the selection signal for each of specific regions in the pixel array.

15. The solid-state imaging device according to claim 14,

wherein, in a part where the specific regions overlap, the exposure control circuit performs control in agreement with a specific region in which a time of charge accumulation to the photoelectric conversion section is shorter.