Memory Device Having Electrically Floating Body Transistor
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Abstract
A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states. A first region of the memory cell is in electrical contact with the floating body region. A second region of the memory cell is spaced apart from the first region and is also in electrical contact with the floating body region. A gate is positioned between the first and second regions. A back-bias region is configured to generate impact ionization when the memory cell is in one of the first and second states, and the back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of the first and second states.
28 Citations
49 Claims
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1-29. -29. (canceled)
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30. A semiconductor memory cell comprising:
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a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; and a back bias region; wherein said floating body region acts as a base region of a first bipolar transistor that maintains the state of said memory cell; wherein said back-bias region acts as a collector region of said first bipolar transistor and has a lower band gap than said floating body region; wherein said floating body region acts as a base region of a second bipolar transistor that is used to perform at least one of reading and writing the state of said memory cell; and wherein current flow through said second bipolar transistor is larger when said memory cell is in one of said first and second states than when said memory cell is in the other of said first and second states. - View Dependent Claims (31, 32, 33, 34, 35, 36)
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37. A semiconductor memory array comprising:
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a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes; a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; and a back bias region; wherein said floating body region acts as a base region of a first bipolar transistor that maintains the state of said memory cell; wherein said back-bias region acts as a collector region of said first bipolar transistor and has a lower band gap than said floating body region; wherein said floating body region acts as a base region of a second bipolar transistor that is used to perform at least one of reading and writing the state of said memory cell; and wherein current flow through said second bipolar transistor is larger when said memory cell is in one of said first and second states than when said memory cell is in the other of said first and second states; wherein said back bias region is commonly connected to at least two of said memory cells - View Dependent Claims (38, 39, 40, 41, 42, 43)
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44. An integrated circuit comprising:
a semiconductor memory array comprising; a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes; a floating body region configured to be charged to a level indicative of a state of the memory cell selected from at least first and second states; and a back bias region; wherein said floating body region acts as a base region of a first bipolar transistor that maintains the state of said memory cell; wherein said back-bias region acts as a collector region of said first bipolar transistor and has a lower band gap than said floating body region; wherein said floating body region acts as a base region of a second bipolar transistor that is used to perform at least one of reading and writing the state of said memory cell; wherein current flow through said second bipolar transistor is larger when said memory cell is in one of said first and second states than when said memory cell is in the other of said first and second states; wherein said back bias region is commonly connected to at least two of said memory cells; and a control circuit configured to provide electrical signals to said back bias region. - View Dependent Claims (45, 46, 47, 48, 49)
Specification