SEMICONDUCTOR DEVICE

• US 20190148559A1
• Filed: 01/10/2019
• Published: 05/16/2019
• Est. Priority Date: 03/27/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: UMEZAKI, Atsushi
• Granted Patent: US 10,297,693 B1
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/04 Structural and physical details of display devices
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line. Duty ratios of the first clock signal and the second clock signal are different from each other. A period during which the second clock signal is changed from an L-level signal to an H-level signal after the first clock signal is changed from an H-level signal to an L-level signal is longer than a period during which the preceding stage signal is changed from an L-level signal to an H-level signal.

Claims

1. (canceled)

2. A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor,

wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the fourth transistor, and a first gate line,

wherein a gate of the first transistor is directly connected to one of a source and a drain of the second transistor, one of a source and a drain of the third transistor, one of a source and a drain of the fifth transistor, and a gate of the sixth transistor,

wherein a gate of the third transistor is directly connected to the other of the source and the drain of the third transistor and a second gate line,

wherein a gate of the fourth transistor is directly connected to a gate of the fifth transistor, one of a source and a drain of the sixth transistor, and one of a source and a drain of the seventh transistor,

wherein a gate of the seventh transistor is directly connected to the other of the source and the drain of the seventh transistor, and

wherein a signal whose potential is changed is input to the other of the source and the drain of the second transistor.

3. The semiconductor device according to claim 2, wherein the first transistor comprises a semiconductor layer comprising amorphous silicon, the semiconductor layer comprising a channel region.

4. A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; and

a capacitor,

wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the fourth transistor, a first electrode of the capacitor, and a first gate line,

wherein a gate of the first transistor is directly connected to one of a source and a drain of the second transistor, one of a source and a drain of the third transistor, one of a source and a drain of the fifth transistor, a gate of the sixth transistor, and a second electrode of the capacitor,

wherein a gate of the third transistor is directly connected to the other of the source and the drain of the third transistor and a second gate line,

wherein a gate of the fourth transistor is directly connected to a gate of the fifth transistor, one of a source and a drain of the sixth transistor, and one of a source and a drain of the seventh transistor,

wherein a gate of the seventh transistor is directly connected to the other of the source and the drain of the seventh transistor,

wherein a signal whose potential is changed is input to the other of the source and the drain of the second transistor,

wherein a channel width of the first transistor is larger than a channel width of each of the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor.

5. The semiconductor device according to claim 4, wherein the first transistor comprises a semiconductor layer comprising amorphous silicon, the semiconductor layer comprising a channel region.

6. A semiconductor device comprising:

a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; and

a capacitor,

wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the fourth transistor, a first electrode of the capacitor, and a first gate line,

wherein a gate of the first transistor is directly connected to one of a source and a drain of the second transistor, one of a source and a drain of the third transistor, one of a source and a drain of the fifth transistor, a gate of the sixth transistor, and a second electrode of the capacitor,

wherein a gate of the third transistor is directly connected to the other of the source and the drain of the third transistor and a second gate line,

wherein a gate of the fourth transistor is directly connected to a gate of the fifth transistor, one of a source and a drain of the sixth transistor, and one of a source and a drain of the seventh transistor,

wherein a gate of the seventh transistor is directly connected to the other of the source and the drain of the seventh transistor,

wherein a signal whose potential is changed is input to the other of the source and the drain of the second transistor,

wherein a channel width of the first transistor is larger than a channel width of each of the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor,

wherein the other of the source and the drain of the first transistor is directly connected to a signal line, and

wherein each of the other of the source and the drain of the fourth transistor, the other of the source and the drain of the fifth transistor, the other of the source and the drain of the sixth transistor is directly connected to a power supply line.

7. The semiconductor device according to claim 6, wherein the first transistor comprises a semiconductor layer comprising amorphous silicon, the semiconductor layer comprising a channel region.