METHODS FOR PHASE-CHANGE MEMORY ARRAY

• US 20190155528A1
• Filed: 01/21/2019
• Published: 05/23/2019
• Est. Priority Date: 12/31/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bedeschi, Ferdinando, Resta, Claudio, Ferraro, Marco
• Granted Patent: US 10,416,909 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/0622 in relation to access
• CPC Class Codes: G06F 3/0643 Management of files
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0059 Security or protection circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 13/02 using elements whose operation depends upon chemical change G11C13/0009 takes precedence
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect

Abstract

Methods of operating phase-change memory arrays are described. A method includes determining a pattern to be written to a phase-change memory array and executing, according to the pattern, two or more proper reset sequences on the phase-change memory array to write the pattern to the phase-change memory array. Another method includes executing a set sequence on a phase-change memory array and performing a proper read of the phase-change memory array to obtain a pattern derived from executing the set sequence.

Claims

1. A method of operating a memory structure, comprising:

determining a pattern to be written to the memory structure, the memory structure comprising multiple memory cells having a storage element including a chalcogenide material, the pattern comprising both real data bits representing data to be stored and fake data bits having a state that is unimportant to the data to be stored; and

writing the pattern to a group of the memory cells.

2. The method of claim 1, wherein the multiple memory cells are variable resistance memory cells.

3. The method of claim 1, wherein the fake data bits are incorporated in a same logic packet as the real data bits.

4. The method of claim 3, wherein the logic packets are selected from at least one packet type including packet types of nibbles, bytes, words, double words, and long words.

5. The method of claim 1, further comprising, prior to storing the real data bits and fake data bits in the group of memory cells, providing one or more reset pulses of a selected characteristic to the memory cells in which the data bits and fake bits will be stored.

6. The method of claim 5, wherein the reset pulses of selected characteristics include hard reset pulses and soft reset pulses, and wherein hard reset pulses have a magnitude greater than that of soft reset pulses.

7. The method of claim 5, comprising providing one or more hard reset pulses to at least the group of memory cells to place the group of memory cells in a first logic state.

8. The method of claim 5, comprising providing one or more soft reset pulses to at least the group of memory cells to place the group of memory cells in a second logic state.

9. The method of claim 2, further comprising, prior to writing the pattern to the group of memory cells, placing the memory cells of the group in a known logic state.

10. The method of claim 5, further comprising writing a logical “

0”

to the group of memory cells using one or more hard reset pulses.

11. The method of claim 5, further comprising writing a logical “

1”

to the group of memory cells using the one or more soft reset pulses.

12. The method of claim 1, further comprising, prior to writing the data bits and fake data bits to the group of memory cells, performing at least two reset operations on at least the group of memory cells, wherein each reset operation comprises providing at least one of, one or more hard reset pulses or one or more soft reset pulses, to the group of memory cells.

13. The method of claim 12, further comprising:

receiving a password associated with a memory operation;

comparing the password to a password stored in the memory structure;

determining a match between the received write password and the stored password; and

in response to determining the match, performing the at least two reset operations can at least the group of memory cells.

14. The method of claim 13, further comprising comparing the password with information stored in a programmable memory to verify a validity of the password relative to the associated memory operation.

15. The method of claim 1, further comprising:

receiving a password associated with a memory operation;

comparing the password to a password stored in the memory structure;

determining a non-match between the received password and the stored password; and

in response to determining the non-match, performing an erase operation on at least the group of memory cells.

16. The method of claim 15, wherein performing the erase operation comprises applying a set pulse to at least the group of memory cells.

17. A system, comprising:

a memory array including multiple memory cells including storage elements comprising a chalcogenide material;

one or more processors coupled to the memory array configured to determine a pattern to be written to a group of memory cells of the memory array, the pattern comprising both real data bits having a state representative of data to be stored, and fake data bits having a state that is unimportant to the data of the real data bits; and

an internal state machine coupled to the memory array and configured to write the pattern to the group of memory cells of memory array.

18. The system of claim 17, wherein the multiple memory cells storage elements comprising a chalcogenide material are variable resistance memory cells.

19. The system of claim 17, wherein the internal state machine is further to perform set and reset sequencing of the memory array.

20. The system of claim 17, wherein the writing of a pattern comprising real data bits and fake data bits operates to encrypt the data of the real data bits.

21. The system of claim 17, further comprising a memory block separate from the memory array, the memory block configured to include system information including passwords for memory operations on the the memory array.

22. The system of claim 21, wherein the one or more processors are further configured to:

compare a received password associated with a requested memory operation to a password stored in the memory structure to determine whether the received password matches the stored password; and

in response the determination, performing one of multiple possible operations on at least the group of memory cells.

23. The system of claim 22, wherein the multiple possible operations comprise:

resetting at least a portion of the memory cells of the memory array to a known logic state; and

erasing at least a portion of the memory cells of the memory array.