FABRICATION OF LOGIC DEVICES AND POWER DEVICES ON THE SAME SUBSTRATE

• US 20190189521A1
• Filed: 12/15/2017
• Published: 06/20/2019
• Est. Priority Date: 12/15/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Li, Juntao, Cheng, Kangguo, Jiang, Liying, Gaudiello, John G.
• Granted Patent: US 10,685,886 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

A method of forming a logic device and a power device on a substrate is provided. The method includes forming a first vertical fin on a first region of the substrate and a second vertical fin on a second region of the substrate, wherein an isolation region separates the first region from the second region, forming a dielectric under-layer segment on the second vertical fin on the second region, and forming a first gate structure on the dielectric under-layer segment and second vertical fin on the second region.

Claims

1. A method of forming a logic device and a power device on a substrate, comprising:

forming a first vertical fin on a first region of the substrate and a second vertical fin on a second region of the substrate, wherein an isolation region separates the first region from the second region;

forming a dielectric under-layer segment on the second vertical fin on the second region;

forming a first gate structure on the dielectric under-layer segment and second vertical fin on the second region; and

forming a top source/drain on each of the first vertical fin and the second vertical fin, wherein the top source/drain on the second vertical fin is above the first gate structure.

2. The method of claim 1, wherein the dielectric under-layer segment has a thickness in a range of about 5 nm to about 10 nm.

3. The method of claim 1, wherein the dielectric under-layer segment is made of a material selected from the group consisting of silicon oxide (SiO), silicon oxynitride (SiON), silicon boro carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), and combinations thereof.

4. The method of claim 1, wherein the first gate structure includes a gate dielectric layer on the dielectric under-layer segment, a work function layer on the gate dielectric layer, and a conductive gate fill on the work function layer.

5. The method of claim 1, further comprising foil ling a second gate structure on the first vertical fin on the first region, wherein the gate structure includes a second gate dielectric layer on the first vertical fin, a second work function layer on the gate dielectric layer, and a second conductive gate fill on the second work function layer.

6. The method of claim 5, forming a bottom spacer layer on the first region of the substrate and the second region of the substrate, wherein the second gate structure on the first vertical fin on the first region includes a horizontal portion of the second gate dielectric layer in physical contact with the bottom spacer layer on the first region of the substrate, and the first gate structure on the second vertical fin on the second region includes a horizontal portion of the first gate dielectric layer in physical contact with the dielectric under-layer segment, and a conductive region on the second region has an inverted T-shape.

7. The method of claim 1, further comprising forming a bottom source/drain region in the substrate under the first vertical fin on the first region, and forming a doped well in the substrate under the second vertical fin on the second region, wherein a bottom source/drain region is not formed in the first doped well under the second vertical fin, and wherein the bottom source/drain region has a dopant concentration of at least 5 times the dopant concentration of the doped well.

9. The method of claim 7, further comprising forming a contact layer on the top source/drains, the doped well, and the bottom source/drain region.

8. (canceled)

10. A method of forming a logic device and a power device on a substrate, comprising:

forming a first vertical fin on a first region of the substrate and a second vertical fin on a second region of the substrate, wherein an isolation region separates the first region from the second region;

forming a first doped well in the substrate under the first vertical fin on the first region and a second doped well in the substrate under the second vertical fin on the second region;

forming a bottom source/drain region in the first doped well, wherein a bottom source/drain region is not formed in the second doped well under the second vertical fin;

forming a dielectric under-layer on the first vertical fin and the second vertical fin;

forming a masking block on the dielectric under-layer and second vertical fin on the second region that leaves a portion of the dielectric under-layer on the first vertical fin exposed;

removing the exposed portion of the dielectric under-layer to form a dielectric under-layer segment on the second vertical fin;

removing the masking block;

forming a gate dielectric layer on the dielectric under-layer segment and first vertical fin on the first region; and

fainting a top source/drain on a top surface of each of the first vertical fin and the second vertical fin.

11. The method of claim 10, wherein the dielectric under-layer segment is made of a material selected from the group consisting of silicon oxide (SiO), silicon oxynitride (SiON), silicon boro carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), and combinations thereof.

12. The method of claim 11, wherein the gate dielectric layer is made of a material selected from the group consisting of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), boron nitride (BN), high-k dielectric materials, and combinations thereof.

13. The method of claim 12, wherein the gate dielectric layer has a thickness in the range of about 7 Å

to about 30 Å

, and the dielectric under-layer segment has a thickness in the range of about 5 nm to about 10 nm.

14. The method of claim 13, further comprising forming a bottom spacer layer on the substrate below the gate dielectric layer and the dielectric under-layer segment.

15. (canceled)

16. A logic device and a power device on a substrate, comprising:

a first vertical fin on a first region of the substrate and a second vertical fin on a second region of the substrate, wherein an isolation region separates the first region from the second region;

a first doped well and a bottom source/drain region in the substrate below the first vertical fin;

a second doped well in the substrate below the second vertical fin;

a bottom spacer layer on the bottom source/drain region and the second doped well;

a dielectric under-layer segment on the bottom spacer layer and the second vertical fin; and

a first gate dielectric layer on the dielectric under-layer segment.

17. The logic device and a power device of claim 16, further comprising a second gate dielectric layer on the bottom spacer layer and the first vertical fin on the first region.

18. The logic device and a power device of claim 17, wherein the first doped well can be a p-type doped well and the second doped well can be an n-type doped well, wherein the n-type doped well has a dopant concentration in the range of about 1×

10¹⁷ atoms/cm³ to about 1×

10¹⁹ atoms/cm³, and the bottom source/drain region has a dopant concentration in the range of about 1×

10¹⁸ atoms/cm³ to about 1×

10²¹ atoms/cm³.

19. The logic device and a power device of claim 18, further comprising a contact layer formed on the n-type doped well, wherein a lateral distance between the contact layer and vertical fin is in a range of about 20 nm to about 200 nm.

20. The logic device and a power device of claim 19, wherein the bottom source/drain region has a dopant concentration of at least 5 times the dopant concentration of the doped well, and the n-type doped well has a depth in a range of about 30 nm to about 150 nm.