PERPENDICULAR SOURCE AND BIT LINES FOR AN MRAM ARRAY

• US 20190206470A1
• Filed: 12/28/2017
• Published: 07/04/2019
• Est. Priority Date: 12/28/2017
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Transfer Technologies, Inc.
• Inventors: BERGER, Neal, LOUIE, Benjamin, EL BARAJI, Mourad, CRUDELE, Lester
• Granted Patent: US 10,395,711 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1697 Power supply circuits
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207

Abstract

A memory device comprising an array of memory cells wherein each memory cell comprises a respective magnetic random access memory (MRAM) element, a respective gating transistor, and a common wordline coupled to gates of gating transistors of said array of memory cells. The memory device further comprises a common source line coupled to sources of said gating transistors, wherein said common source line is routed perpendicular to said plurality of bit lines within said array of memory cells, and a plurality of bit lines which are routed parallel to each other and connected to the drains of said gating transistors, wherein each bit line is associated with a respective memory cell of said array of memory cells.

Claims

1. A memory device comprising:

an array of memory cells wherein each memory cell comprises;

a respective magnetic random access memory (MRAM) element; and

a respective gating transistor;

a common wordline coupled to gates of gating transistors of said array of memory cells;

a common source line coupled to sources of said gating transistors, wherein said common source line is routed perpendicular to said plurality of bit lines within said array of memory cells; and

a plurality of bit lines which are routed parallel to each other and connected to the drains of said gating transistors, wherein each bit line is associated with a respective memory cell of said array of memory cells, wherein to store a data bit of a first logical value, a voltage polarity of said common source line is held at a mid level voltage and an addressed bit line is asserted to ground and wherein, to store a data bit of a second logical value, said common source line is held to said mid level voltage and said addressed bit line is asserted at a voltage higher than said mid level voltage.

2. A memory device as described in claim 1 wherein said desired voltage on said common source line is operable to be used in conjunction with an active bit line of said plurality of bit lines to program a data value into an addressed memory cell of said memory array, wherein said addressed memory cell corresponds to said active bit line.

5. A memory device as described in claim 2 wherein each respective MRAM element of said memory array is coupled, at a first end thereof, to a respective bit line of said plurality of bit lines, and further coupled, at a second end thereof, to a drain of a respective gating transistor and wherein further said respective gating transistor comprises a gate coupled to said common wordline and a source coupled to said common source line.

6. A memory device as described in claim 2 wherein, an addressed memory cell, of said array of memory cells, is operable to be programmed with a data bit by:

making active said wordline; and

making active a bit line, of said plurality of bit lines, that corresponds to said addressed memory cell while remainder bit lines of said plurality of bit lines remain inactive.

8. A memory array as described in claim 2 wherein said respective magnetic random access memory (MRAM) element comprises a magnetic tunnel junction (MTJ).

3. (canceled)

4. (canceled)

7. (canceled)

9. A memory device comprising:

an array of memory cells wherein each memory cell comprises;

a respective magnetic random access memory (MRAM) element; and

a respective gating transistor;

a plurality of bit lines which are routed parallel to each other, wherein each bit line is associated with a respective memory cell of said array of memory cells;

a common word line coupled to gates of gating transistors of said array of memory cells; and

a common source line coupled to sources of said gating transistors, wherein said common source line is routed perpendicular to said plurality of bit lines within said array of memory cells, wherein said array of memory cells is operable to store a data bit into an addressed memory cell of said array of memory cells responsive to a voltage applied between said common source line and an addressed bit line of said plurality of bit lines while said common word line is active, and wherein said addressed bit line is associated with said addressed memory cell, wherein, to store said data bit of a first logical value, a voltage polarity of said common source line is held at a mid level voltage and said addressed bit line is asserted to ground and wherein, to store said data bit of a second logical value, said common source line is held to said mid level voltage and said addressed bit line is asserted at a voltage higher than said mid level voltage.

13. A memory device as described in claim 9 wherein each respective MRAM element of said memory array is coupled, at a first end thereof, to a respective bit line of said plurality of bit lines, and further coupled, at a second end thereof, to a drain of a respective gating transistor and wherein further said respective gating transistor comprises a gate coupled to said common word line and a source coupled to said common source line.

10. (canceled)

11. (canceled)

12. (canceled)

14. A method for programming a memory device, said method comprising:

selecting a bit line of a memory cell of an array;

selecting a source line of the memory cell of the array, wherein the selected bit line and the selected source line are disposed perpendicularly to one another;

driving a word line coupled to a gate of a gating transistor to activate the memory cell;

wherein, to store a data bit of a first logical value, holding a voltage polarity of a common source line at a mid level voltage and asserting an addressed bit line to ground and wherein, to store a data bit of a second logical value, holding said common source line to said mid level voltage and asserting said addressed bit line at a voltage higher than said mid level voltage.

15. A method for programming a memory device as described in claim 14 wherein said voltage polarity of said common source line is operable to be used in conjunction with an active bit line of said plurality of bit lines to program a data value into an addressed memory cell of said memory array, wherein said addressed memory cell corresponds to said active bit line.

18. A method for programming a memory device as described in claim 15 wherein each respective MRAM element of said memory array is coupled, at a first end thereof, to a respective bit line of said plurality of bit lines, and further coupled, at a second end thereof, to a drain of a respective gating transistor and wherein further said respective gating transistor comprises a gate coupled to said common wordline and a source coupled to said common source line.

19. A method for programming a memory device as described in claim 15, wherein the memory cell is part of an array of memory cells, wherein each memory cell of said array of memory cells comprises:

a respective magnetic random access memory (MRAM) element; and

a respective gating transistor;

said plurality of bit lines routed parallel to each other, wherein each bit line is associated with a respective memory cell of said array of memory cells;

said common word line coupled to gates of gating transistors of said array of memory cells; and

said common source line coupled to sources of said gating transistors, wherein said common source line is routed perpendicular to said plurality of bit lines within said array of memory cells.

16. (canceled)

17. (canceled)

20. (canceled)