APPARATUSES AND METHODS FOR CALCULATING ROW HAMMER REFRESH ADDRESSES IN A SEMICONDUCTOR DEVICE

• US 20190228815A1
• Filed: 01/22/2018
• Published: 07/25/2019
• Est. Priority Date: 01/22/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Morohashi, Masaru, Noguchi, Hidekazu
• Granted Patent: US 10,580,475 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/1636 using refresh
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 15/04 using semiconductor elements
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 8/10 Decoders

Abstract

An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.

Claims

1. An apparatus comprising:

a logic circuit configured to responsive to first information to provide second information,

wherein the first information comprises a first plurality of bits, less significant bits of the first information including first, second, third and fourth bits, the first bit being a least significant bit of the first plurality of bits;

wherein the second information comprises a second plurality of bits, less significant bits of the second information comprising fifth, sixth, seventh and eighth bits, the fifth bit being a least significant bit of the second plurality of bits;

wherein the logic circuit is further configured;

to perform a logical inversion on the first bit to provide the fifth bit,

to perform a first logical operation on first, second, third and fourth bits to provide the sixth bit,

to perform a second logical operation on first, second, third and fourth bits to provide the seventh bit, and

to perform a third logical operation on first, second, third and fourth bits to provide the eighth bit; and

wherein the first, second and third logical operations are different from one another.

2. The apparatus of claim 1, wherein the logic circuit is configured responsive to the first information to provide third information;

wherein the third information comprises a third plurality of bits, less significant bits of the third information comprising, ninth, tenth, eleventh and twelfth bits, the ninth bit being a least significant bit of the third plurality of bits;

wherein the logic circuit is further configured;

to perform a logical inversion on the first bit to provide the ninth bit; and

to output the second, third and fourth bits as the tenth, eleventh and twelfth bits.

3. The apparatus of claim 2, further comprising a memory cell array including a plurality of first memory cells coupled to a first word line, a plurality of second memory cells coupled to a second word line arranged directly adjacent to the first word line and a plurality of third memory cells coupled to a third word line arranged directly adjacent to the first word line;

wherein the first word line is selected based on the first information, the second word line is selected based on the second information and the third word line is selected based on the third information.

4. The apparatus of claim 2, wherein the logic circuit includes first and second circuit portions different from each other and each of the first, second and third logical operations is performed based at least in part on the first and second circuit portions.

5. The apparatus of claim 4, wherein outputs from the first and second circuit portions are disabled when the logic circuit provides the third information responsive to the first information.

6. The apparatus of claim 1, wherein the logic circuit comprises an address scrambler circuit configured to receive the first information in response to detection of a row hammer attack.

7. The apparatus of claim 6, wherein the first information comprises a row hammer hit address and the second information comprises a row hammer refresh address calculated from the row hammer hit address.

8. An apparatus comprising:

an address scrambler circuit comprising a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address, wherein the sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, wherein the sub-wordline scrambler circuit is further configured to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.

9. The apparatus of claim 8, wherein the sub-wordline scrambler circuit is configured to perform bitwise exclusive OR operations on individual bits of the first subset of bits and respective individual bits of the second subset of bits to provide the third subset of bits.

10. The apparatus of claim 8, wherein the first set of logical operations performed by the sub-wordline scrambler circuit comprise bitwise exclusive OR comparisons on first, second, and fourth bits of the first subset of bits and bitwise exclusive OR comparisons on second and third bits of the first subset of bits.

11. The apparatus of claim 8, wherein the sub-wordline scrambler circuit is configured to perform a third set of logical operations on the first subset of bits to calculate a fourth subset of bits of a second row hammer refresh address.

12. The apparatus of claim 8, wherein the sub-wordline scrambler circuit is configured to calculate a carry bit based on a value of the first subset of bits, and wherein the address scrambler circuit further comprises a plurality of row hammer counter circuits each configured to convert a respective bit of a remaining subset of bits of the row hammer hit address to a respective bit of a remaining subset of the row hammer refresh address based on the carry bit.

13. The apparatus of claim 12, wherein a first row hammer counter circuit of the plurality of row hammer counter circuits comprises an XOR logic gate configured to perform an exclusive OR operation on a bit of the remaining subset of bits of the row hammer hit address and the carry bit to provide a first bit of the remaining subset of bits of the row hammer refresh address.

14. The apparatus of claim 13, wherein the first row hammer counter circuit of the plurality of row hammer counter circuits comprises a second XOR logic gate configured to perform an exclusive OR operation on the carry bit and a polarity bit indicating addition or subtraction to provide a second carry bit to a second row hammer counter circuit of the plurality of row hammer counter circuits.

15. A method comprising:

receiving a first subset of bits of a row hammer hit address at an address scrambler circuit;

performing a first set of logical operations on the first subset of bits to provide a second subset of bits; and

performing a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of a row hammer refresh address.

16. The method of claim 15, wherein performing the first set of logical operations on the first subset of bits to provide the second subset of bits comprises:

performing a first logical operation on first, second, third and fourth bits of the first subset of bits to provide a second bit of the second subset of bits,

performing a second logical operation on the first, second, third and fourth bits of the first subset of bits to provide a third bit of the second subset of bits, and

performing a third logical operation on the first, second, third and fourth bits of the first subset of bits to provide a fourth bit of the second subset of bits.

17. The method of claim 16, wherein the first, second and third logical operations comprise:

performing a first bitwise exclusive OR operation on the first, second, and fourth bits of the first subset of bits; and

performing a second bitwise exclusive OR operation on the second and third bits of the first subset of bits.

18. The method of claim 15, wherein performing the second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of the row hammer refresh address comprises:

performing a logical inversion on the first bit of the first subset of bits to provide a first bit of the third subset of bits.

performing a first logical operation on a second bit of the first subset of bits and a second bit of the second subset of bits to provide a second bit of the third subset of bits;

performing a second logical operation on a third bit of the first subset of bits and a third bit of the second subset of bits to provide a third bit of the third subset of bits, and

performing a third logical operation on a fourth bit of the first subset of bits and a fourth bit of the second subset of bits to provide a fourth bit of the third subset of bits.

19. The method of claim 18, wherein the first, second and third logical operations comprises common logical operations.

20. The method of claim 18, wherein the first, second and third logical operations comprise performing bitwise exclusive OR operations.