SEMICONDUCTOR DEVICE

• US 20190244884A1
• Filed: 09/10/2018
• Published: 08/08/2019
• Est. Priority Date: 02/02/2018
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: YOON, Sung Young, CHO, Yong Sang, HA, Sang Su
• Granted Patent: US 10,643,935 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/1411 the bump connectors being bonded to at least one common bonding area
• CPC Class Codes: H01L 2224/14131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/14505 Bump connectors having different materials
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A semiconductor device includes a semiconductor chip including a gate structure, the semiconductor chip having a first region and a second region that surrounds sides of the first region, first solder balls on the first region of the semiconductor chip and containing a first weight percent of silver, second solder balls on the first region of the semiconductor chip and containing a second weight percent of silver greater than the first weight percent, and third solder balls on the second region of the semiconductor chip and containing a third weight percent of silver less than the first weight percent.

Claims

1. A semiconductor device, comprising:

a semiconductor chip including a gate structure, the semiconductor chip having a first region and a second region that surrounds sides of the first region;

first solder balls on the first region of the semiconductor chip and containing a first weight percent of silver;

second solder balls on the first region of the semiconductor chip and containing a second weight percent of silver greater than the first weight percent; and

third solder balls on the second region of the semiconductor chip and containing a third weight percent of silver less than the first weight percent.

2. The semiconductor device as claimed in claim 1, further comprising a redistribution layer on the first region of the semiconductor chip, electrically connected to the second solder balls, and electrically insulated from the first solder balls and the third solder balls.

3. The semiconductor device as claimed in claim 2, wherein the redistribution layer includes a first redistribution layer electrically connected to one of the second solder balls, and a second redistribution layer electrically connected to another one of the second solder balls and is spaced apart from the first redistribution layer.

4. The semiconductor device as claimed in claim 3, wherein a top surface of the gate structure includes a first part that overlaps the first redistribution layer, a second part that overlaps the second redistribution layer, and a third part between the first and second parts that does not overlap the first and second redistribution layers.

5. The semiconductor device as claimed in claim 1, wherein:

the first solder balls have a first degree of thermal expansion,

the second solder balls have a second degree of thermal expansion greater than the first degree of thermal expansion, and

the third solder balls have a third degree of expansion less than the first degree of thermal expansion.

6. The semiconductor device as claimed in claim 5, wherein:

the first solder balls have a first hardness,

the second solder balls have a second hardness greater than the first hardness, and

the third solder balls have a third hardness less than the first hardness.

7. The semiconductor device as claimed in claim 1, wherein:

the first solder balls contain a fourth weight percent of tin,

the second solder balls contain a fifth weight percent of tin less than the fourth weight percent, and

the third solder balls contain a sixth weight percent of tin greater than the fourth weight percent.

8. The semiconductor device as claimed in claim 7 wherein the first solder balls, the second solder balls, and the third solder balls all have a same copper content.

9. The semiconductor device as claimed in claim 1, wherein:

the first solder balls contain a seventh weight percent of copper,

the second solder balls contain an eighth weight percent of copper less than the seventh weight percent, and

the third solder balls contain a ninth weight percent of copper greater than the seventh weight percent.

10. The semiconductor device as claimed in claim 9, wherein the first solder balls, the second solder balls, and the third solder balls all have a same tin content.

11. A semiconductor device, comprising:

a semiconductor chip including a gate structure, the semiconductor chip having a first region and a second region that surrounds sides of the first region;

a redistribution layer on the first region of the semiconductor chip;

first solder balls on the first region of the semiconductor chip, electrically insulated from the redistribution layer, and having a first degree of thermal expansion;

second solder balls on the first region of the semiconductor chip, electrically connected to the redistribution layer, and having a second degree of thermal expansion greater than the first degree of thermal expansion; and

third solder balls on the second region of the semiconductor chip, electrically insulated from the redistribution layer, and having a third degree of thermal expansion less than the first degree of thermal expansion.

12. The semiconductor device as claimed in claim 11, wherein:

the first solder balls have a first hardness,

the second solder balls have a second hardness greater than the first hardness, and

the third solder balls have a third hardness less than the first hardness.

13. The semiconductor device as claimed in claim 11, wherein:

the first solder balls contain a first weight percent of silver,

the second solder balls contain a second weight percent of silver greater than the first weight percent, and

the third solder balls contain a third weight percent of silver less than the first weight percent.

14. The semiconductor device as claimed in claim 11, wherein:

the first solder balls contain a fourth weight percent of tin,

the second solder balls contain a fifth weight percent of tin less than the fourth weight percent, and

the third solder balls contain a sixth weight percent of tin greater than the fourth weight percent.

15. The semiconductor device as claimed in claim 11, wherein:

the first solder balls contain a seventh weight percent of copper,

the second solder balls contain an eighth weight percent of copper less than the seventh weight percent, and

the third solder balls contain a ninth weight percent of copper greater than the seventh weight percent.

16. The semiconductor device as claimed in claim 11, wherein a top surface of the gate structure does not overlap the redistribution layer.

17. A semiconductor device, comprising:

a semiconductor chip including a gate structure, the semiconductor chip having a first region and a second region that surrounds sides of the first region;

a redistribution layer on the first region of the semiconductor chip;

first solder balls on the first region of the semiconductor chip, electrically insulated from the redistribution layer, and having a first hardness;

second solder balls on the first region of the semiconductor chip, electrically connected to the redistribution layer, and having a second hardness greater than the first hardness; and

third solder balls on the second region of the semiconductor chip, electrically insulated from the redistribution layer, and having a third hardness less than the first hardness.

18. The semiconductor device as claimed in claim 17, wherein:

the first solder balls have a first degree of thermal expansion,

the second solder balls have a second degree of thermal expansion greater than the first degree of thermal expansion, and

the third solder balls have a third degree of expansion less than the first degree of thermal expansion.

19. The semiconductor device as claimed in claim 17, wherein:

the first solder balls contain a first weight percent of silver,

the second solder balls contain a second weight percent of silver greater than the first weight percent, and

the third solder balls contain a third weight percent of silver less than the first weight percent.

20. The semiconductor device as claimed in claim 17, wherein a top surface of the gate structure completely overlaps the redistribution layer.