SEMICONDUCTOR DEVICE

• US 20190259828A1
• Filed: 05/01/2019
• Published: 08/22/2019
• Est. Priority Date: 08/20/2012
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: NAKANO, Yuki, NAKAMURA, Ryota, SAKAIRI, Hiroyuki
• Granted Patent: US 10,580,852 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The semiconductor device includes: a semiconductor layer in which a trench is formed having a side surface and a bottom surface; a second conductivity-type layer formed on the semiconductor layer on the side surface and the bottom surface of the trench; a first conductivity-type layer formed on the semiconductor layer so as to contact the second conductivity-type layer; a first electrode electrically connected to the first conductivity-type layer; a second electrode embedded in the trench and electrically connected to the second conductivity-type layer; and a barrier-forming layer which is arranged between the second electrode and the side surface of the trench and which, between said barrier-forming layer and the second conductivity-type layer, forms a potential barrier higher than the potential barrier between the second conductivity-type layer and the second electrode.

Claims

1-27. -27. (canceled)

28. A semiconductor device comprising:

a semiconductor layer in which a first trench having a side surface and a bottom surface and a second trench having a side surface and a bottom surface are formed;

a first conductivity layer of a first conductivity type that is exposed from a surface of the semiconductor layer and that forms the side surface of the first trench and the side surface of the second trench;

a second conductivity layer of a second conductivity type that is disposed on a back surface side of the semiconductor layer with respect to the first conductivity layer such that the second conductivity layer is in contact with the first conductivity layer, and that forms a part of the side surface of the first trench and a part of the side surface of the second trench;

a third conductivity layer of the first conductivity type that is disposed on the back surface side of the semiconductor layer with respect to the second conductivity layer such that the third conductivity layer is in contact with the second conductivity layer, and that forms the bottom surface of the first trench and the bottom surface of the second trench;

a first electrode that is embedded in the first trench;

a first insulating film disposed between the side and bottom surfaces of the first trench and the first electrode;

a second electrode that is embedded in the second trench and that is electrically connected to the first conductivity layer;

a third electrode that is electrically connected to the third conductivity layer; and

a breakdown voltage holding layer that is formed in the semiconductor layer and that forms the side and bottom surfaces of the second trench.

29. The semiconductor device according to claim 28, wherein the side surface of the second trench is inclined to the bottom surface of the second trench by an obtuse angle.

30. The semiconductor device according to claim 28, further comprising a MOSFET including a source layer formed by the first conductivity layer, a channel layer formed by the second conductivity layer, and a drain layer formed by the third conductivity layer.

31. The semiconductor device according to claim 30, wherein

the first trench includes a gate trench formed in the MOSFET, and

the second trench includes a source trench formed in the MOSFET.

32. The semiconductor device according to claim 28, wherein the semiconductor layer includes an SiC semiconductor layer.

33. The semiconductor device according to claim 28, wherein the second trench has a depth deeper than a lower portion of the first conductivity layer.

34. The semiconductor device according to claim 28, wherein the second trench has a depth deeper than a lower portion of the second conductivity layer.

35. The semiconductor device according to claim 28, wherein the first trench is shallower than the second trench.

36. The semiconductor device according to claim 28, further comprising a hetero junction diode formed at a joint surface between the second electrode and the third conductivity layer.

37. The semiconductor device according to claim 36, wherein the hetero junction diode has a junction barrier smaller than a diffusion potential of a body diode formed by pn junction between the second conductivity layer and the third conductivity layer.

38. The semiconductor device according to claim 37, wherein

the junction barrier of the hetero junction diode is 1 eV to 1.5 eV, and

the diffusion potential of the body diode is 2.8 eV to 3.2 eV.

39. The semiconductor device according to claim 28, further comprising a barrier-forming layer having a potential barrier higher than a potential barrier between the breakdown voltage holding layer and the second electrode.

40. The semiconductor device according to claim 28, wherein the first electrode is made of polysilicon.

41. The semiconductor device according to claim 28, wherein the second electrode is electrically connected to the breakdown voltage holding layer.

42. The semiconductor device according to claim 28, further comprising an insulating layer disposed on the side surface of the second trench and an edge portion of the bottom surface of the second trench.

43. The semiconductor device according to claim 42, wherein the second electrode has a polysilicon layer at least on the insulating layer.

44. The semiconductor device according to claim 41, wherein the insulating layer is disposed such that the first conductivity layer is exposed from the side surface of the second trench.

45. The semiconductor device according to claim 42, wherein the polysilicon layer is embedded in a region inside the insulating layer in the second trench, and

the second electrode includes a metal layer stacked on the polysilicon layer embedded in the region.

46. The semiconductor device according to claim 41, wherein the insulating layer is made of any one of non-doped polysilicon, silicon oxide (SiO₂), aluminum oxide (Al₂O₃), and aluminum oxynitride (AlON).

47. The semiconductor device according to claim 41, wherein the side surface of the second trench is covered with the insulating layer in a region ranging from the bottom surface of the second trench to an opening end of the second trench in a depth direction.