Latency-based Scheduling of Command Processing in Data Storage Devices

• US 20190265909A1
• Filed: 02/28/2018
• Published: 08/29/2019
• Est. Priority Date: 02/28/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Frolikov, Alex
• Granted Patent: US 10,489,085 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A computer system having a host coupled to a storage device via a peripheral component interconnect express bus. The host communicates write commands of low priority to the storage device, which places them in a queue for execution at an idle time. In response to a determination that the storage device is in an idle state, the storage device best accommodates the write commands in the idle queue in connection with housekeeping tasks, such as garbage collection and wear leveling, to best reduce write amplification.

Claims

1. A storage device, comprising:

a host interface;

a controller;

non-volatile storage media; and

firmware containing instructions executable by the controller to;

receive, via the host interface, a plurality of commands from a host,

select a subset of commands from the plurality of commands;

schedule the subset for execution during an idle time; and

reduce write amplification in executing the commands in the subset during the idle time.

2. The storage device of claim 1, wherein the non-volatile storage media includes flash memory;

and the controller performs garbage collection during the idle time.

3. The storage device of claim 2, wherein the commands of the subset include write commands for storing data in the flash memory.

4. The storage device of claim 3, wherein the write commands are executed after performing garbage collection.

5. The storage device of claim 3, wherein the write commands are executed in combination with garbage collection.

6. The storage device of claim 3, wherein the commands of the subset are scheduled in a queue for execution during the idle time in response to the host identifying that the commands of the subset have no requirement in latency performance in completion.

7. The storage device of claim 6, wherein the write commands are selected for the queue based on an attribute of the write commands.

8. The storage device of claim 7, wherein the attribute indicates that the write commands stores data non-sequentially in an address space.

9. The storage device of claim 3, wherein the write commands in the subset are scheduled in a queue for execution during the idle time in response to the host specifying a priority level lower than a threshold for the write commands.

10. The storage device of claim 3, wherein the write commands in the subset are scheduled in a queue for execution during the idle time in response to the host specifying a quality of service level lower than a threshold for the commands of the subset.

11. The storage device of claim 2, wherein the controller reduces write amplification via compressing data to be stored via the commands in the subset.

12. The storage device of claim 2, wherein the controller reduces write amplification via combining write operations in the commands in the subset.

13. The storage device of claim 2, wherein the controller reduces write amplification via searching a logical to physical address map schedule for execution of the commands in the subset via minimizing write amplification.

14. The storage device of claim 1, wherein the host interface communicates with the host via a peripheral component interconnect express bus in accordance with a non-volatile memory host controller interface specification.

15. The storage device of claim 14, wherein the host has a plurality of submission queues to communicate requests to the storage device;

and the storage device is determined to be in the idle state at least after the submission queues are empty.

16. A method implemented in a storage device, the method comprising:

receiving, via a host interface of the storage device, a plurality of commands from a host,

selecting, by a controller executing firmware, a subset of commands from the plurality of commands;

scheduling, by the controller, the subset for execution during an idle time; and

reducing, by the controller, write amplification in non-volatile storage media of the storage device in executing the commands in the subset during the idle time.

17. The method of claim 16, wherein reducing write amplification includes searching for a logical to physical address map to minimize write operations.

18. The method of claim 16, wherein reducing write amplification includes combining write operations of the commands in the subset.

19. The method of claim 16, wherein reducing write amplification includes compressing data of the commands in the subset using a technique different from a compression technique used for commands executed at a non-idle time.

20. A non-transitory computer storage medium storing instructions which, when executed by a storage device, cause the storage device to perform a method, the method comprising:

receiving, via a host interface of the storage device, a plurality of commands from a host,

selecting, by a controller executing firmware, a subset of commands from the plurality of commands;

scheduling, by the controller, the subset for execution during an idle time; and

reducing, by the controller, write amplification in non-volatile storage media of the storage device in executing the commands in the subset during the idle time.