METHOD FOR MANUFACTURING AN ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE

• US 20190273164A1
• Filed: 08/10/2017
• Published: 09/05/2019
• Est. Priority Date: 08/19/2016
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: CHEN, Jiangbo, DU, Jianhua, WANG, Guoying, LIU, Wei
• Granted Patent: US 10,644,162 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02592 amorphous
• CPC Class Codes: H01L 21/383 using diffusion into or out of a solid from or into a gaseous phase
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/247 Amorphous materials
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H10K 59/00 Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/126 Shielding, e.g. light-blocking means over the TFTs
• CPC Class Codes: H10K 59/1315 comprising structures specially adapted for lowering the resistance

Abstract

A method for manufacturing an array substrate, a display panel and a display device are provided. The method includes forming a semiconductor layer, a gate insulating layer, a gate and an inter-layer insulator successively on a base substrate; forming via holes in the inter-layer insulator so as to expose portions of the semiconductor layer; performing plasma bombardment to the portions of the semiconductor layer exposed in the via holes; forming a source electrode and a drain electrode coupled with the semiconductor layer through the via holes respectively on the inter-layer insulator.

Claims

1. A method for manufacturing an array substrate, comprising:

forming a semiconductor layer, a gate insulating layer, a gate and an inter-layer insulator successively on a base substrate;

forming via holes in the inter-layer insulator so as to expose portions of the semiconductor layer;

performing plasma bombardment to the portions of the semiconductor layer exposed in the via holes;

forming a source electrode and a drain electrode coupled with the semiconductor layer through the via holes respectively on the inter-layer insulator.

2. The method according to claim 1, wherein a material of forming the semiconductor layer is determined based on a preset contact resistance, wherein the contact resistance is a resistance generated by contact of the source electrode or the drain electrode with the semiconductor layer.

3. The method according to claim 1, wherein a time of the plasma bombardment is in negative correlation with a contact resistance, wherein the contact resistance is a resistance generated by contact of the source electrode or the drain electrode with the semiconductor layer.

4. The method according to claim 1, wherein the semiconductor layer is formed by amorphous InGaZnO, and an oxygen content of the amorphous InGaZnO is in negative correlation with a contact resistance, wherein the contact resistance is a resistance generated by contact of the source electrode or the drain electrode with the semiconductor layer.

5. The method according to claim 1, wherein a flux of the plasma bombardment is in negative correlation with a contact resistance, wherein the contact resistance is a resistance generated by contact of the source electrode or the drain electrode with the semiconductor layer.

6. The method according to claim 1, wherein an intensity of the plasma bombardment is in negative correlation with a contact resistance, wherein the contact resistance is a resistance generated by contact of the source electrode or the drain electrode with the semiconductor layer.

7. The method according to claim 1, wherein a gas used in the plasma bombardment is selected from helium, nitrogen, ammonia and hydrogen.

8. The method according to claim 1, wherein forming via holes in the inter-layer insulator comprises:

performing dry etching to the inter-layer insulator by carbon tetrafluoride and oxygen.

9. The method according to claim 1, wherein a thickness of the inter-layer insulator formed is greater than or equal to about 100 nanometers and less than or equal to about 500 nanometers.

10. The method according to claim 1, wherein, after forming the gate and before forming the inter-layer insulator, the method further comprises:

forming a source region and a drain region in regions of the semiconductor layer that are not covered, the source region and the drain region receiving an external electric signal through the source electrode and the drain electrode respectively.

11. The method according to claim 1, wherein, before forming the semiconductor layer, the method further comprises forming a light shielding layer on the base substrate.

12. The method according to claim 11, wherein, before forming the semiconductor layer and after forming the light shielding layer, the method further comprises forming a buffer layer on the light shielding layer.

13. The method according to claim 1, wherein, after forming the source electrode and the drain electrode, the method further comprises forming a passivation layer on the source electrode and the drain electrode.

14. A display panel, comprising an array substrate manufactured by the method as claimed in claim 1.

15. A display device, comprising the display panel as claimed in claim 14.

16. The display panel according to claim 14, wherein a material of forming the semiconductor layer is determined based on a preset contact resistance, wherein the contact resistance is a resistance generated by contact of the source electrode or the drain electrode with the semiconductor layer.

17. The display panel according to claim 14, wherein a time of the plasma bombardment is in negative correlation with a contact resistance, wherein the contact resistance is a resistance generated by contact of the source electrode or the drain electrode with the semiconductor layer.

18. The display panel according to claim 14, wherein the semiconductor layer is formed by amorphous InGaZnO, and an oxygen content of the amorphous InGaZnO is in negative correlation with a contact resistance, wherein the contact resistance is a resistance generated by contact of the source electrode or the drain electrode with the semiconductor layer.

19. The display panel according to claim 14, wherein a flux of the plasma bombardment is in negative correlation with a contact resistance, wherein the contact resistance is a resistance generated by contact of the source electrode or the drain electrode with the semiconductor layer.

20. The display panel according to claim 14, wherein an intensity of the plasma bombardment is in negative correlation with a contact resistance, wherein the contact resistance is a resistance generated by contact of the source electrode or the drain electrode with the semiconductor layer.