SEMICONDUCTOR DEVICE HAVING FIN STRUCTURES OF VARYING DIMENSIONS
First Claim
1. A semiconductor device, comprising:
- at least one first fin having a first width;
a first gate electrode crossing the first fin;
a first gate dielectric layer between the first fin and the first gate electrode and having a first thickness;
at least one second fin having a second width greater than the first width;
a second gate electrode crossing the second fin; and
a second gate dielectric layer between the second fin and the second gate electrode and having a second thickness less than the first thickness.
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Accused Products
Abstract
A semiconductor device includes at least one first fin, a first gate, a first gate dielectric layer, at least one second fin, a second gate electrode, and a second gate dielectric layer. The first fin has a first width. The first gate electrode crosses the first fin. The first gate dielectric layer is between the first fin and the first gate electrode and has a first thickness. The second fin has a second width greater than the first width. The second gate electrode crosses the second fin. The second gate dielectric layer is between the second fin and the second gate electrode and has a second thickness less than the first thickness.
40 Citations
24 Claims
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1. A semiconductor device, comprising:
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at least one first fin having a first width; a first gate electrode crossing the first fin; a first gate dielectric layer between the first fin and the first gate electrode and having a first thickness; at least one second fin having a second width greater than the first width; a second gate electrode crossing the second fin; and a second gate dielectric layer between the second fin and the second gate electrode and having a second thickness less than the first thickness. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A semiconductor device, comprising:
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a first n-well region; a second n-well region spaced apart from the first n-well region; a plurality of first fins located within the first n-well region and arranged along a first direction by a first pitch, wherein at least one of the first fins has a first width; a first gate electrode crossing the first fins and extending along a second direction orthogonal to the first direction; a plurality of second fins located within the second n-well region and arranged along the first direction by a second pitch equal to the first pitch, wherein at least one of the second fins has a second width greater than the first width; and a second gate electrode crossing the second fins and extending along the second direction. - View Dependent Claims (14, 15, 16, 24)
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17-20. -20. (canceled)
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21. A semiconductor device comprising:
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an I/O circuit including a first transistor, wherein the first transistor includes a plurality of first fins that have a first width, and a first gate electrode over the plurality of the first fins; and a core circuit including a second transistor, wherein the second transistor includes a single second fin that has a second width greater than the first width, and a second gate electrode over the single second fin. - View Dependent Claims (22, 23)
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Specification