Positive Logic Switch with Selectable DC Blocking Circuit

  • US 20190305767A1
  • Filed: 03/28/2018
  • Published: 10/03/2019
  • Est. Priority Date: 03/28/2018
  • Status: Active Grant
First Claim
Patent Images

1. A stack of FET switches, at least one FET switch requiring a negative VGS to turn OFF and configured so as to not require a negative power supply, series-coupled on at least one end to an end-cap FET that turns OFF when the VGS of such end-cap FET is essentially zero volts.

View all claims

    Thank you for your feedback