Positive Logic Switch with Selectable DC Blocking Circuit

• US 20190305767A1
• Filed: 03/28/2018
• Published: 10/03/2019
• Est. Priority Date: 03/28/2018
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Inventors: Ranta, Tero Tapio, Willard, Simon Edward
• Granted Patent: US 10,505,530 B2
• Time in Patent Office: Days
• CPC Class Codes: H03K 17/0412 by measures taken in the control circuit
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 17/6874 in a symmetrical configuration
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 2017/066 Maximizing the OFF-resistance instead of minimizing the ON-resistance
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its V_GS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero V_GS type, or a mix of positive-logic and zero V_GS type FETs with end-cap FETs of the zero V_GS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

Claims

1. A stack of FET switches, at least one FET switch requiring a negative V_GS to turn OFF and configured so as to not require a negative power supply, series-coupled on at least one end to an end-cap FET that turns OFF when the V_GS of such end-cap FET is essentially zero volts.

2. A stack of FET switches, including at least one positive-logic FET requiring a negative V_GS to turn OFF and configured so as to not require a negative power supply, series-coupled on at least one end to an end-cap FET that turns OFF when the V_GS of such end-cap FET is essentially zero volts.

6. The invention of claim 2, wherein each end-cap FET functions as a DC blocking capacitor when in an OFF state, and as a resistive signal path when in an ON state.

17. The invention of claim 2, further including a negative gate bias voltage supply coupled to the gates of the end-cap FETs.

3. A FET switch stack, including:

(a) one or more positive-logic FETs requiring a negative V_GS to turn OFF and configured so as to not require a negative power supply; and

(b) a first end-cap FET that turns OFF when the V_GS of the first end-cap FET is essentially zero volts, series-coupled to a first end of the one or more series-coupled positive-logic FETs.

4. The invention of claim 3, further including a second end-cap FET that turns OFF when the V_GS of the second end-cap FET is essentially zero volts, series-coupled to a second end of the one or more series-coupled positive-logic FETs.

5. The invention of claim 3, further including at least one additional FET that turns OFF when the V_GS of such FET is essentially zero volts, series coupled to the FET switch stack.

7. The invention of claim 3, further including at least one capacitor coupled between the source and the drain of a corresponding end-cap FET.

8. The invention of claim 3, further including a gate bias resistor ladder including a plurality of series-coupled resistors configured to be coupled to a gate bias voltage, wherein each resistor is coupled to the respective gates of corresponding adjacent FETs.

9. The invention of claim 8, further including a capacitor coupled between the gate bias resistor ladder and a reference potential.

10. The invention of claim 8, further including an AC coupling gate module coupled to at least one end of the gate bias resistor ladder and configured to be coupled to a radio frequency voltage source.

11. The invention of claim 10, wherein the AC coupling gate module includes one of a capacitor or a capacitor series coupled to a resistor.

12. The invention of claim 3, further including a body charge control resistor ladder including a plurality of resistors configured to be coupled to a body bias voltage, wherein each resistor is coupled to the body of at least one corresponding FET.

13. The invention of claim 12, further including a capacitor coupled between the body charge control resistor ladder and a reference potential.

14. The invention of claim 12, further including an AC coupling body module coupled to at least one end of the body charge control resistor ladder and configured to be coupled to a radio frequency voltage source.

15. The invention of claim 14, wherein the AC coupling body module includes one of a capacitor or a capacitor series coupled to a resistor.

16. The invention of claim 3, further including a drain-source resistor ladder including a plurality of series-coupled resistors configured to be coupled to a drain-source bias voltage, wherein each resistor is coupled to the respective drains and sources of corresponding adjacent positive-logic FETs.

18. The invention of claim 3, wherein at least one FET is an ACS FET.

19-38. -38. (canceled)