Positive Logic Switch with Selectable DC Blocking Circuit
First Claim
1. A stack of FET switches, at least one FET switch requiring a negative V_{GS }to turn OFF and configured so as to not require a negative power supply, seriescoupled on at least one end to an endcap FET that turns OFF when the V_{GS }of such endcap FET is essentially zero volts.
1 Assignment
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Accused Products
Abstract
A positivelogic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising seriescoupled positivelogic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), seriescoupled on at least one end by an “endcap” FET of a type that turns OFF when its V_{GS }is zero volts. The one or more endcap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero V_{GS }type, or a mix of positivelogic and zero V_{GS }type FETs with endcap FETs of the zero V_{GS }type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drainsource resistors, body charge control resistors, and one or more AC coupling modules.
4 Citations
19 Claims

1. A stack of FET switches, at least one FET switch requiring a negative V_{GS }to turn OFF and configured so as to not require a negative power supply, seriescoupled on at least one end to an endcap FET that turns OFF when the V_{GS }of such endcap FET is essentially zero volts.
 2. A stack of FET switches, including at least one positivelogic FET requiring a negative V_{GS }to turn OFF and configured so as to not require a negative power supply, seriescoupled on at least one end to an endcap FET that turns OFF when the V_{GS }of such endcap FET is essentially zero volts.

3. A FET switch stack, including:

(a) one or more positivelogic FETs requiring a negative V_{GS }to turn OFF and configured so as to not require a negative power supply; and (b) a first endcap FET that turns OFF when the V_{GS }of the first endcap FET is essentially zero volts, seriescoupled to a first end of the one or more seriescoupled positivelogic FETs.  View Dependent Claims (4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18)


1938. 38. (canceled)
1 Specification