Stacked FET Switch Bias Ladders
First Claim
1. A FET switch stack, including:
 (a) a plurality of seriescoupled FETs;
(b) a gate bias resistor ladder including a plurality of resistors configured to be coupled to a gate bias voltage and to the gate of at least one corresponding FET;
(c) a body charge control resistor ladder including a plurality of resistors configured to be coupled to a body bias voltage and to the body of at least one corresponding FET; and
(d) a drainsource resistor ladder including a plurality of seriescoupled resistors configured to be coupled to a drainsource bias voltage, wherein each resistor is coupled to the respective drains and sources of at least one corresponding adjacent FET;
wherein the resistors of the gate bias resistor ladder are seriesconnected and the resistors of the body charge control resistor ladder are parallelconnected; and
wherein the plurality of seriescoupled FETs includes one or more seriescoupled positivelogic FETs requiring a relative negative V_{GS }to turn OFF but configured to not require a negative power supply, and a first endcap FET that turns OFF when the V_{GS }of such first endcap FET is essentially zero volts, seriescoupled to a first end of the one or more seriescoupled positivelogic FETs.
1 Assignment
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Accused Products
Abstract
A positivelogic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising seriescoupled positivelogic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), seriescoupled on at least one end by an “endcap” FET of a type that turns OFF when its V_{GS }is zero volts. The one or more endcap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero V_{GS }type, or a mix of positivelogic and zero V_{GS }type FETs with endcap FETs of the zero V_{GS }type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drainsource resistors, body charge control resistors, and one or more AC coupling modules.
5 Citations
17 Claims

1. A FET switch stack, including:

(a) a plurality of seriescoupled FETs; (b) a gate bias resistor ladder including a plurality of resistors configured to be coupled to a gate bias voltage and to the gate of at least one corresponding FET; (c) a body charge control resistor ladder including a plurality of resistors configured to be coupled to a body bias voltage and to the body of at least one corresponding FET; and (d) a drainsource resistor ladder including a plurality of seriescoupled resistors configured to be coupled to a drainsource bias voltage, wherein each resistor is coupled to the respective drains and sources of at least one corresponding adjacent FET; wherein the resistors of the gate bias resistor ladder are seriesconnected and the resistors of the body charge control resistor ladder are parallelconnected; and wherein the plurality of seriescoupled FETs includes one or more seriescoupled positivelogic FETs requiring a relative negative V_{GS }to turn OFF but configured to not require a negative power supply, and a first endcap FET that turns OFF when the V_{GS }of such first endcap FET is essentially zero volts, seriescoupled to a first end of the one or more seriescoupled positivelogic FETs.  View Dependent Claims (4, 5, 6, 8, 10, 13, 14)


2. A FET switch stack, including:

(a) a plurality of seriescoupled FETs; (b) a gate bias resistor ladder including a plurality of resistors configured to be coupled to a gate bias voltage and to the gate of at least one corresponding FET; (c) a body charge control resistor ladder including a plurality of resistors configured to be coupled to a body bias voltage and to the body of at least one corresponding FET; and (d) a drainsource resistor ladder including a plurality of seriescoupled resistors configured to be coupled to a drainsource bias voltage, wherein each resistor is coupled to the respective drains and sources of at least one corresponding adjacent FET; wherein the resistors of the gate bias resistor ladder are parallelconnected and the resistors of the body charge control resistor ladder are seriesconnected; and wherein the plurality of seriescoupled FETs includes one or more seriescoupled positivelogic FETs requiring a relative negative V_{GS }to turn OFF but configured to not require a negative power supply, and a first endcap FET that turns OFF when the V_{GS }of such first endcap FET is essentially zero volts, seriescoupled to a first end of the one or more seriescoupled positivelogic FETs.


3. (canceled)

7. (canceled)

9. (canceled)

11. (canceled)

12. (canceled)

15. A FET switch stack, including:

(a) a plurality of seriescoupled FETs having a first FET configured to be coupled to a radio frequency (RF) signal input; (b) a first gate resistor ladder including a plurality of parallelconnected constantvalued resistors each coupled to the gate of one corresponding FET; and (c) a second gate bias resistor ladder including a plurality of seriesconnected variablevalued resistors each coupled to one corresponding constantvalued resistor of the first gate resistor ladder and having resistive values that taper from higher resistive values to lower resistive values, with the higher resistive values located near the RF signal input to the first FET.


16. A FET switch stack, including:

(a) a plurality of seriescoupled FETs having a first FET configured to be coupled to a radio frequency (RF) signal input; (b) a first gate resistor ladder including a plurality of parallelconnected variablevalued resistors each coupled to the gate of one corresponding FET; and (c) a second gate bias resistor ladder including a plurality of seriesconnected variablevalued resistors each coupled to one corresponding constantvalued resistor of the first gate resistor ladder and having resistive values that taper from higher resistive values to lower resistive values, with the higher resistive values located near the RF signal input to the first FET.


1732. 32. (canceled)
1 Specification