Stacked FET Switch Bias Ladders

  • US 20190305768A1
  • Filed: 03/28/2018
  • Published: 10/03/2019
  • Est. Priority Date: 03/28/2018
  • Status: Active Grant
First Claim
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1. A FET switch stack, including:

  • (a) a plurality of series-coupled FETs;

    (b) a gate bias resistor ladder including a plurality of resistors configured to be coupled to a gate bias voltage and to the gate of at least one corresponding FET;

    (c) a body charge control resistor ladder including a plurality of resistors configured to be coupled to a body bias voltage and to the body of at least one corresponding FET; and

    (d) a drain-source resistor ladder including a plurality of series-coupled resistors configured to be coupled to a drain-source bias voltage, wherein each resistor is coupled to the respective drains and sources of at least one corresponding adjacent FET;

    wherein the resistors of the gate bias resistor ladder are series-connected and the resistors of the body charge control resistor ladder are parallel-connected; and

    wherein the plurality of series-coupled FETs includes one or more series-coupled positive-logic FETs requiring a relative negative VGS to turn OFF but configured to not require a negative power supply, and a first end-cap FET that turns OFF when the VGS of such first end-cap FET is essentially zero volts, series-coupled to a first end of the one or more series-coupled positive-logic FETs.

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