AC Coupling Modules for Bias Ladders

• US 20190305769A1
• Filed: 01/29/2019
• Published: 10/03/2019
• Est. Priority Date: 03/28/2018
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Inventors: Willard, Simon Edward, Ranta, Tero Tapio
• Granted Patent: US 10,630,280 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H03K 17/0412 by measures taken in the control circuit
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 17/6874 in a symmetrical configuration
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 2017/066 Maximizing the OFF-resistance instead of minimizing the ON-resistance
• CPC Class Codes: H03K 2217/0009 AC switches, i.e. delivering AC power to a load
• CPC Class Codes: H03K 2217/0054 Gating switches, e.g. pass gates

Abstract

A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its V_GS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero V_GS type, or a mix of positive-logic and zero V_GS type FETs with end-cap FETs of the zero V_GS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

Claims

1. 1. A method for providing a FET switch stack, including:

(a) providing a plurality of series-coupled FETs, including a first end FET having a first signal terminal and a second end FET having a second signal terminal;

(b) coupling a gate bias resistor ladder to the gates of the series-coupled FETs, the gate bias resistor ladder configured to be coupled to a gate control voltage that controls the ON or OFF switch state of each series-coupled FET; and

(c) coupling an AC coupling gate module to at least one end of the gate bias resistor ladder and configuring the AC coupling gate module to be coupled to a radio frequency voltage source;

wherein in response to the OFF switch state of each series-coupled FET, a signal applied to the first or second signal terminal is blocked from conduction through the plurality of series-coupled FETs, and wherein in response to the ON switch state of each series-coupled FET, a signal applied to the first or second signal terminal is conducted through the plurality of series-coupled FETs.

2. The method of claim 1, wherein the plurality of series-coupled FETs includes one or more series-coupled positive-logic FET, series-coupled on at least one end to a first end-cap FET that turns OFF when the V_GS of the first end-cap FET is essentially zero volts.

3. The method of claim 2, further including providing a second end-cap FET that turns OFF when the VGS of the second end-cap FET is essentially zero volts, series-coupled to a second end of the one or more series-coupled positive-logic FETs.

4. The method of claim 2, further including providing a drain-source resistor ladder including a plurality of series-coupled resistors configured to be coupled to a drain-source bias voltage, wherein each resistor is coupled to the respective drains and sources of corresponding adjacent positive-logic FETs.

5. The method of claim 1, wherein the gate bias resistor ladder includes a plurality of series-connected resistors.

6. The method of claim 1, wherein the AC coupling gate module includes one of a capacitor or a capacitor series coupled to a resistor.

7. The method of claim 1, wherein the gate bias resistor ladder is configured to be coupled to a bias voltage at a node at a first end of the gate bias resistor ladder.

8. The method of claim 1, wherein the gate bias resistor ladder is configured to be coupled to a bias voltage at a node between a first end and a second end of the gate bias resistor ladder.

9. The method of claim 1, wherein at least one FET is an ACS FET.

10. A method for providing a FET switch stack, including:

(a) providing a plurality of series-coupled FETs;

(b) coupling a gate bias resistor ladder to the gates of the series-coupled FETs;

(c) coupling an AC coupling gate module to at least one end of the gate bias resistor ladder and configuring the AC coupling gate module to be coupled to a corresponding radio frequency voltage source;

(d) coupling a body charge control resistor ladder to the bodies of the series-coupled FETs; and

(e) coupling an AC coupling body module to at least one end of the body charge control resistor ladder and configuring the AC coupling body module to be coupled to the corresponding radio frequency voltage source.

11. The method of claims 10, wherein the plurality of series-coupled FETs includes one or more series-coupled positive-logic FET, series-coupled on at least one end to a first end-cap FET that turns OFF when the V_GS of the first end-cap FET is essentially zero volts.

12. The method of claim 11, further including providing a second end-cap FET that turns OFF when the VGS of the second end-cap FET is essentially zero volts, series-coupled to a second end of the one or more series-coupled positive-logic FETs.

13. The method of claim 11, further including providing a drain-source resistor ladder including a plurality of series-coupled resistors configured to be coupled to a drain-source bias voltage, wherein each resistor is coupled to the respective drains and sources of corresponding adjacent positive-logic FETs.

14. The method of claims 10, wherein the gate bias resistor ladder includes a plurality of series-connected resistors.

15. The method of claim 10, wherein the body charge control resistor ladder includes a plurality of series-connected resistors.

16. The method of claims 10, wherein the AC coupling gate module includes one of a capacitor or a capacitor series coupled to a resistor.

17. The method of claim 10, wherein the AC coupling body module includes one of a capacitor or a capacitor series coupled to a resistor.

18. The method of claims 10, wherein the gate bias resistor ladder is configured to be coupled to a bias voltage at a node at a first end of the gate bias resistor ladder.

19. The method of claims 10, wherein the gate bias resistor ladder is configured to be coupled to a bias voltage at a node between a first end and a second end of the gate bias resistor ladder.

20. The method of claims 10, wherein at least one FET is an ACS FET.