Manufacturing Method of Via Hole, Display Substrate, and Manufacturing Method Thereof

• US 20190311943A1
• Filed: 03/22/2018
• Published: 10/10/2019
• Est. Priority Date: 05/12/2017
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectric Technology Co. Ltd. (BOE Technology Group Co., Ltd.)
• Original Assignee: Hefei Xinsheng Optoelectric Technology Co. Ltd. (BOE Technology Group Co., Ltd.)
• Inventors: WAN, Yunhai, YANG, Chengshao, WANG, Wenlong, CAO, Ke
• Granted Patent: US 10,872,807 B2
• Time in Patent Office: Days
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate

Abstract

A manufacturing method of a via hole, a display substrate and a manufacturing method thereof are provided. The manufacturing method of a via hole includes: forming a first via hole penetrating the passivation protection layer, the first via hole being defined by a first side wall of the passivation protection layer; forming an organic insulating layer on the passivation protection layer; and forming a second via hole penetrating the organic insulating layer, the second via hole being defined by a second side wall of the organic insulating layer; wherein in a sectional view, a bottom of the second via hole is located in the first via hole and is in direct contact with the conductive layer, and the second side wall of the organic insulating layer is separated from the first side wall of the passivation protection layer.

Claims

1. A manufacturing method of a via hole, comprising:

forming a passivation protection layer on a conductive layer;

forming a first via hole penetrating the passivation protection layer, the first via hole being defined by a first side wall of the passivation protection layer;

forming an organic insulating layer on the passivation protection layer; and

forming a second via hole penetrating the organic insulating layer, the second via hole being defined by a second side wall of the organic insulating layer, wherein

in a sectional view, a bottom of the second via hole is located in the first via hole and is in direct contact with the conductive layer, and the second side wall of the organic insulating layer is separated from the first side wall of the passivation protection layer.

2. The manufacturing method of the via hole according to claim 1, wherein a material of the organic insulating layer is a photoresist material.

3. The manufacturing method of the via hole according to claim 2, wherein forming the second via hole penetrating the organic insulating layer comprises:

exposing the organic insulating layer by utilizing a first mask; and

developing the organic insulating layer thus exposed, to form the second via hole.

4. The manufacturing method of the via hole according to claim 3, wherein forming the first via hole penetrating the passivation protection layer comprises:

coating a photoresist on the passivation protection layer;

exposing the photoresist by utilizing a second mask;

developing the photoresist thus exposed;

etching the passivation protection layer to form the first via hole; and

removing the remaining photoresist.

5. The manufacturing method of the via hole according to claim 4, wherein the first mask and the second mask are a same one mask.

7. The manufacturing method of the via hole according to claim 1, wherein the conductive layer is a drain electrode of a thin film transistor of a display substrate.

8. A manufacturing method of a display substrate, comprising the manufacturing method of the via hole according to claim 1.

9. The manufacturing method of the display substrate according to claim 8, wherein the conductive layer is a source-drain electrode layer,

before forming the passivation protection layer on the conductive layer, the manufacturing method of the display substrate further comprises:

sequentially forming a gate electrode, a gate insulating layer, an active layer and the source-drain electrode layer on a base substrate,

after forming the second via hole penetrating the organic insulating layer, the manufacturing method of a display substrate further comprises;

forming a pixel electrode on the organic insulating layer, the pixel electrode being connected to a drain electrode of the source-drain electrode layer through the second via hole;

forming a passivation insulating layer on the pixel electrode; and

forming a common electrode on the passivation insulating layer.

12. The manufacturing method of the via hole according to claim 5, wherein an amount of light exposure utilized in exposing the organic insulating layer is 80%˜

90% of an amount of light exposure utilized in exposing the photoresist.

13. The manufacturing method of the via hole according to claim 2, wherein the conductive layer is a drain electrode of a thin film transistor of a display substrate.

14. The manufacturing method of the via hole according to claim 3, wherein the conductive layer is a drain electrode of a thin film transistor of a display substrate.

15. The manufacturing method of the via hole according to claim 4, wherein the conductive layer is a drain electrode of a thin film transistor of a display substrate.

16. The manufacturing method of the via hole according to claim 5, wherein the conductive layer is a drain electrode of a thin film transistor of a display substrate.

18. The manufacturing method of the via hole according to claim 12, wherein the conductive layer is a drain electrode of a thin film transistor of a display substrate.

6. The manufacturing method of the via hole according to claim, wherein an amount of light exposure utilized in exposing the organic insulating layer is 80%˜

90% of an amount of light exposure utilized in exposing the photoresist.

17. The manufacturing method of the via hole according to claim 6, wherein the conductive layer is a drain electrode of a thin film transistor of a display substrate.

10. A display substrate, comprising:

a base substrate; and

a source-drain electrode layer, a passivation protection layer, an organic insulating layer and a pixel electrode located on the base substrate, the source-drain electrode layer comprising a drain electrode, wherein the first via hole penetrates the passivation protection layer, and the first via hole is defined by a first side wall of the passivation protection layer;

a portion of the organic insulating layer is filled in the first via hole;

the second via hole penetrates the organic insulating layer, and the second via hole is defined by a second side wall of the organic insulating layer, wherein in a sectional view, a bottom of the second via hole is located in the first via hole and is in direct contact with the conductive layer, and the second side wall of the organic insulating layer is separated from the first side wall of the passivation protection layer.

11. The display substrate according to claim 10, further comprising:

a gate electrode, a gate insulating layer and an active layer located between the base substrate and the source-drain electrode layer and sequentially stacked; and

a passivation insulating layer and a common electrode located on the pixel electrode and sequentially stacked.