COMMUNICATION BETWEEN AN IMAGE FORMING DEVICE AND A REPLACEABLE SUPPLY ITEM

• US 20190320085A1
• Filed: 04/12/2018
• Published: 10/17/2019
• Est. Priority Date: 04/12/2018
• Status: Active Grant

• Current Assignee: Lexmark International Incorporated (Ninestar Corporation)
• Original Assignee: Lexmark International Incorporated (Ninestar Corporation)
• Inventors: FOLEY, NATHAN WAYNE, WILLIAMS, JENNIFER TOPMILLER, WOODS, GREGORY SCOTT, Moore, JR., Jimmy Daniel
• Granted Patent: US 10,659,649 B2
• Time in Patent Office: Days
• CPC Class Codes: G03G 15/0865 Arrangements for supplying new developer
• CPC Class Codes: G03G 15/556 for toner consumption, e.g. pixel counting, toner coverage detection or toner density measurement
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 3/121 Facilitating exception or error detection and recovery, e.g. fault, media or consumables depleted
• CPC Class Codes: H04N 1/2346 according to a detected condition or state of the reproducing device, e.g. temperature or ink quantity
• CPC Class Codes: H04N 1/32587 Controller

Abstract

A toner container installable in an image forming device having a controller according to one example embodiment includes a housing having a reservoir for storing toner. A chip is positioned on the housing and configured to receive a first write command from the controller of the image forming device. The chip is further configured to determine whether a transmission cycle bit of the first write command matches a transmission cycle bit of a second write command received by the chip from the controller of the image forming device previous to the first write command. The chip is further configured to resend to the controller of the image forming device a response to the second write command if the transmission cycle bit of the first write command matches the transmission cycle bit of the second write command.

Claims

1. A toner container installable in an image forming device having a controller, comprising:

a housing having a reservoir for storing toner; and

a chip positioned on the housing and configured to receive a first write command from the controller of the image forming device, the chip further configured to determine whether a transmission cycle bit of the first write command matches a transmission cycle bit of a second write command received by the chip from the controller of the image forming device previous to the first write command, the chip further configured to resend to the controller of the image forming device a response to the second write command if the transmission cycle bit of the first write command matches the transmission cycle bit of the second write command.

2. The toner container of claim 1, further comprising the chip configured to execute the first write command and to send to the controller of the image forming device a response to the first write command if the transmission cycle bit of the first write command does not match the transmission cycle bit of the second write command.

3. The toner container of claim 1, further comprising the chip configured to determine whether a command ID of the first write command matches a command ID of the second write command if the transmission cycle bit of the first write command matches the transmission cycle bit of the second write command and to perform said resend to the controller of the image forming device the response to the second write command if the command ID of the first write command matches the command ID of the second write command.

4. The toner container of claim 3, further comprising the chip configured to send an error message to the controller of the image forming device if the command ID of the first write command does not match the command ID of the second write command.

5. The toner container of claim 3, wherein the chip configured to determine whether the command ID of the first write command matches the command ID of the second write command includes the chip configured to determine whether the command ID of the first write command indicates that the first write command is a request from the controller of the image forming device for the chip to send a response to a most recent write command received by the chip from the controller of the image forming device prior to the chip indicating a busy condition to the controller of the image forming device.

6. A chip configured for communication with a controller of an image forming device and mountable on a replaceable supply item for installation in the image forming device, comprising a processor and a memory;

the memory storing program instructions for execution by the processor including instructions to receive a first write command from the controller of the image forming device, to compare a value of a transmission cycle bit contained in a header of the first write command with a value of a transmission cycle bit contained in a header of a second write command received by the processor from the controller of the image forming device previous to the first write command, and to send to the controller of the image forming device a response to the second write command without executing the first write command if the value of the transmission cycle bit contained in the header of the first write command is equal to the value of the transmission cycle bit contained in the header of the second write command.

7. The chip of claim 6, further comprising the memory including instructions to execute the first write command and to send to the controller of the image forming device a response to the first write command if the value of the transmission cycle bit contained in the header of the first write command is not equal to the value of the transmission cycle bit contained in the header of the second write command.

8. The chip of claim 6, further comprising the memory including instructions to compare a value of a command ID of the first write command with a value of a command ID of the second write command if the value of the transmission cycle bit contained in the header of the first write command is equal to the value of the transmission cycle bit contained in the header of the second write command and to perform said send to the controller of the image forming device the response to the second write command without executing the first write command if the value of the command ID of the first write command is equal to the value of the command ID of the second write command.

9. The chip of claim 8, further comprising the memory including instructions to send an error message to the controller of the image forming device if the value of the command ID of the first write command is not equal to the value of the command ID of the second write command.

10. The chip of claim 8, wherein the instructions to compare the value of the command ID of the first write command with the value of the command ID of the second write command include instructions to determine whether the value of the command ID of the first write command indicates that the first write command is a request from the controller of the image forming device for the processor to send a response to a most recent write command received by the processor from the controller of the image forming device prior to the processor indicating a busy condition to the controller of the image forming device.

11. A chip for use on a replaceable supply item of an image forming device, comprising processing circuitry configured to communicate as a slave node of an I2C communication bus with a controller of the image forming device as a master node of the I2C communication bus, the processing circuitry configured to receive a write command from the controller of the image forming device, to determine whether a transmission cycle bit of the received write command matches a transmission cycle bit of a preceding write command received by the processing circuitry from the controller of the image forming device, and to resend to the controller of the image forming device a response to the preceding write command upon the processing circuitry receiving a read command from the controller of the image forming device corresponding to the received write command if the transmission cycle bit of the received write command matches the transmission cycle bit of the preceding write command.

12. The chip of claim 11, further comprising the processing circuitry configured to execute the received write command and to send to the controller of the image forming device a response to the received write command upon receiving the read command from the controller of the image forming device corresponding to the received write command if the transmission cycle bit of the received write command does not match the transmission cycle bit of the preceding write command.

13. The chip of claim 11, further comprising the processing circuitry configured to determine whether a command ID of the received write command matches a command ID of the preceding write command if the transmission cycle bit of the received write command matches the transmission cycle bit of the preceding write command and to perform said resend to the controller of the image forming device the response to the preceding write command upon receiving the read command from the controller of the image forming device corresponding to the received write command if the command ID of the received write command matches the command ID of the preceding write command.

14. The chip of claim 13, further comprising the processing circuitry configured to send an error message to the controller of the image forming device upon receiving the read command from the controller of the image forming device corresponding to the received write command if the command ID of the received write command does not match the command ID of the preceding write command.

15. The chip of claim 13, wherein the processing circuitry configured to determine whether the command ID of the received write command matches the command ID of the preceding write command includes the processing circuitry configured to determine whether the command ID of the received write command indicates that the received write command is a request from the controller of the image forming device for the processing circuitry to send a response to a most recent write command received by the processing circuitry from the controller of the image forming device prior to the processing circuitry indicating a busy condition to the controller of the image forming device.