SHALLOW TRENCH TEXTURED REGIONS AND ASSOCIATED METHODS

• US 20190333959A1
• Filed: 07/08/2019
• Published: 10/31/2019
• Est. Priority Date: 06/29/2013
• Status: Active Grant

• Current Assignee: SiOnyx, LLC (Black Silicon Holdings, Inc.)
• Original Assignee: SiOnyx, LLC (Black Silicon Holdings, Inc.)
• Inventors: HADDAD, Homayoon, JIANG, Jutao
• Granted Patent: US 11,069,737 B2
• Time in Patent Office: Days
• CPC Class Codes: B23K 26/355 Texturing
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 27/14625 Optical elements or arrangements associated with the device
• CPC Class Codes: H01L 27/14629 Reflectors
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 31/02327 the optical elements being integrated or being directly associated to the device, e.g. back reflectors optical coatings H01L31/0216
• CPC Class Codes: H01L 31/028 including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/182 Special manufacturing methods for polycrystalline Si, e.g. Si ribbon, poly Si ingots, thin films of polycrystalline Si

Abstract

Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor layer having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor layer and positioned to interact with electromagnetic radiation. The textured region can be formed from a series of shallow trench isolation features.

Claims

1. An optoelectronic device having enhanced absorption of electromagnetic radiation, comprising:

a semiconductor layer coupled to a support substrate; and

an array of shallow trench isolation surface features positioned between the semiconductor layer and the support substrate, the surface features positioned to interact with electromagnetic radiation that passes through the semiconductor layer.

2. The device of claim 1, wherein the semiconductor layer is single crystal silicon.

3. The device of claim 1, further comprising a first bonding layer coupled between the semiconductor layer and the support substrate.

4. The device of claim 3, wherein the first bonding layer is coupled between the support substrate and the surface features.

5. The device of claim 3, further comprising a second bonding layer positioned between the first bonding layer and the support substrate.

6. The device of claim 5, further comprising a reflector layer disposed between the first bonding layer and the second bonding layer.

7. The device of claim 1, wherein the surface features are formed in the support substrate.

8. The device of claim 1, wherein the surface features are formed in the semiconductor layer.

9. The device of claim 1, wherein the surface features are arranged according to a predetermined pattern.

10. The device of claim 9, wherein the predetermined pattern is an at least substantially uniform grid.

11. The device of claim 9, wherein the predetermined pattern is a non-uniform arrangement.

12. The device of claim 1, wherein the surface features have an at least substantially uniform height.

13. The device of claim 1, wherein the surface features are not uniform in height.

14. The device of claim 1, further comprising a device layer coupled to the semiconductor layer on a side opposite the surface features.

15. The device of claim 1, wherein the device is architecturally configured as a front-side illuminated optoelectronic device.

16. The device of claim 1, wherein the device is architecturally configured as a back-side illuminated optoelectronic device.

17. A method of making an optoelectronic device, comprising:

creating an array of surface features on a semiconductor layer using shallow trench isolation etching; and

bonding the array of surface features between a support substrate and a semiconductor layer.

18. The method of claim 17, wherein creating the array of surface features further comprises creating the array of surface features on at least a portion of a surface of the semiconductor layer.

19. The method of claim 17, wherein creating the array of surface features further comprises creating the array of surface features on at least a portion of a surface of the support substrate.

20. The method of claim 17, wherein bonding the array of surface features between the support substrate and the semiconductor layer further includes:

depositing a first bonding layer onto the semiconductor layer; and

bonding the first bonding layer to a second bonding layer disposed on the support substrate.