TECHNIQUES FOR CONTACT FORMATION IN SELF-ALIGNED REPLACMENT GATE DEVICE

• US 20190348509A1
• Filed: 05/11/2018
• Published: 11/14/2019
• Est. Priority Date: 05/11/2018
• Status: Active Grant

• Current Assignee: Varian Semiconductor Equipment Associates Incorporated (Applied Materials Incorporated)
• Original Assignee: Varian Semiconductor Equipment Associates Incorporated (Applied Materials Incorporated)
• Inventors: Sung, Min Gyu, Wang, Wenhui, Lee, Jun, Varghese, Sony
• Granted Patent: US 10,644,117 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02244 of a metallic layer
• CPC Class Codes: H01L 21/02252 formation by plasma treatment, e.g. plasma oxidation of the substrate after treatment of an insulating film by plasma H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 21/32115 Planarisation
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method may include providing a device structure, where the device structure includes a semiconductor region, and a gate structure, disposed over the semiconductor region. The gate structure may further include a gate metal. The method may further include oxidizing an upper portion of the gate metal, wherein the upper portion forms an oxide cap, and wherein a lower portion of the gate metal remains metallic.

Claims

1. A method, comprising:

providing a device structure, the device structure comprising;

a semiconductor region, and

a gate structure, disposed over the semiconductor region, the gate structure comprising a gate metal; and

oxidizing an upper portion of the gate metal, wherein the upper portion forms an oxide cap, and wherein a lower portion of the gate metal remains metallic.

2. The method of claim 1, the gate metal comprising tungsten.

3. The method of claim 1, the oxidizing comprising performing a plasma oxidation.

4. The method of claim 3, wherein the plasma oxidation comprises generating oxygen ions and directing the oxygen ions to the device structure at an ion energy of 500 eV to 10 keV.

5. The method of claim 1, further comprising forming a source/drain contact to the semiconductor region.

6. The method of claim 5, further comprising planarizing the upper portion after the oxidizing and before the forming the source/drain contact.

7. The method of claim 6, wherein the planarizing comprises selectively etching the oxide cap.

8. The method of claim 1, wherein the gate structure comprises a tungsten gate metal, a nitride sidewall spacer, disposed along the tungsten gate metal, and wherein the device structure further comprises a dielectric, disposed outside the nitride sidewall spacer, the method further comprising:

selectively etching a top region of the oxide cap, wherein a bottom region of the oxide cap remains above the lower portion of the gate metal after the selectively etching.

9. A method, comprising:

forming a device structure, the device structure comprising;

a semiconductor fin;

a gate structure, disposed over a first portion of the semiconductor fin, the gate structure comprising a gate metal and a set of sidewall spacers; and

a source/drain structure, disposed over a second portion of the semiconductor fin;

oxidizing an upper portion of the gate metal, wherein the upper portion forms an oxide cap, and wherein a lower portion of the gate metal remains metallic; and

selectively removing a top region of the oxide cap, wherein a bottom region of the oxide cap remains above the lower portion of the gate metal.

10. The method of claim 9, the gate metal comprising tungsten.

11. The method of claim 9, the forming the device structure comprising:

forming a dummy gate structure, the dummy gate structure comprising a sacrificial gate material and the set of sidewall spacers;

selectively removing the sacrificial gate material; and

replacing the sacrificial gate material with a gate metal, wherein the gate metal extends above the set of sidewall spacers; and

polishing the gate metal to remove a portion of the gate metal extending above the set of sidewall spacers.

12. The method of claim 9, the oxidizing comprising performing a plasma oxidation.

13. The method of claim 12, wherein the plasma oxidation comprises generating oxygen ions and directing the oxygen ions to the device structure at an ion energy of 500 eV to 10000 eV.

14. The method of claim 9, wherein the oxide cap extends above the set of sidewall spacers after the oxidizing, and wherein the selectively removing the top region comprises planarizing the oxide cap with respect to the set of sidewall spacers.

15. The method of claim 9, wherein the gate structure comprises a tungsten gate metal, a nitride sidewall spacer, disposed along the tungsten gate metal, and wherein the device structure further comprises a dielectric, disposed outside the nitride sidewall spacer, wherein the oxide cap comprises a tungsten oxide, wherein the selectively removing the oxide comprises selectively etching the tungsten oxide with respect to the nitride sidewall spacer and the dielectric.

16. A method, comprising:

providing a device structure, the device structure comprising;

a semiconductor fin, and

a gate structure, disposed over the semiconductor fin, the gate structure comprising a tungsten gate metal and a set of sidewall spacers;

oxidizing an upper portion of the tungsten gate metal, wherein the upper portion forms a tungsten oxide, and wherein a lower portion of the tungsten gate metal remains metallic; and

selectively removing a top region of the tungsten oxide, wherein a bottom region of the tungsten oxide remains above the lower portion of the tungsten gate metal.

17. The method of claim 16, wherein the tungsten oxide extends above the set of sidewall spacers after the oxidizing, and wherein the selectively removing the top region comprises planarizing the oxide with respect to the set of sidewall spacers.

18. The method of claim 16, wherein the gate structure comprises a nitride sidewall spacer, disposed along the tungsten gate metal, and wherein the device structure further comprises a dielectric, disposed outside the nitride sidewall spacer, wherein the selectively removing the top region of the tungsten oxide comprises selectively etching the tungsten oxide with respect to the nitride sidewall spacer and the dielectric.