MEMORY DEVICE CONFIGURATION COMMANDS

• US 20190369889A1
• Filed: 08/15/2019
• Published: 12/05/2019
• Est. Priority Date: 09/14/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Siciliani, Umberto, Siviero, Anna Chiara, Smaniotto, Andrea
• Granted Patent: US 10,585,606 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Apparatuses and methods for configuring a memory device using configuration commands are provided. One example method can include executing a first command while the memory device is in a ready state to configure the memory device to a particular mode and executing a second command to perform a first operation while the memory device is in the particular mode.

Claims

1. An apparatus, comprising:

an array of memory cells of a memory device; and

a processing device coupled to the array of memory cells, the processing device configured to;

execute a command, while the memory device is in a ready state, to configure the memory device to a particular mode, wherein the particular mode defines a particular programming algorithm.

2. The apparatus of claim 1, wherein the processing device is configured to execute the command to configure the memory device to the particular mode by configuring the memory device to include a number of bits per cell.

3. The apparatus of claim 1, wherein the processing device is configured to execute another command to perform an operation while the memory device in the particular mode.

4. The apparatus of claim 1, wherein the processing device is configured to execute the command to configure the memory device to the particular mode by configuring the memory device to a single level cell mode.

5. The apparatus of claim 1, wherein the processing device is configured to execute the command to configure the memory device to the particular mode by configuring the memory device to a multi-level cell mode.

6. The apparatus of claim 1, wherein the processing device is configured to execute another command to configure the memory device to another mode different from the particular mode.

7. The apparatus of claim 1, wherein the processing device is configured to execute another command to perform an operation on a first logical unit (LUN) of the memory device while the memory device is in the particular mode.

8. An apparatus, comprising:

an array of memory cells of a memory device; and

a processing device coupled to the array of memory cells, the processing device configured to;

receive a command including instructions to configure the memory device to a particular mode, wherein the particular mode defines a particular programming algorithm; and

execute the command to configure the memory device to the particular mode while the memory device in a ready state.

9. The apparatus of claim 8, wherein the processing device is configured to execute the command without transferring data on a data bus between the memory device and a host.

10. The apparatus of claim 8, wherein the processing device is configured to execute another command to write data to the memory device.

11. The apparatus of claim 8, wherein the processing device is configured to execute another command to read data from the memory device.

12. The apparatus of claim 8, wherein the processing device is configured to execute another command to erase data from the memory device.

13. A system, comprising:

a host configured to send a first and a second command; and

a memory device coupled to the host, wherein the memory device comprises;

an array of memory cells; and

a processing device coupled to the array of memory cells, wherein the processing device is configured to;

execute the first command to configure the memory device to a particular mode while the memory device in a ready state, wherein the particular mode defines a particular programming algorithm; and

execute the second command to perform while the memory device is in the particular mode.

14. The system of claim 13, wherein the processing device is configured to execute a third command to configure the memory device to another mode different from the particular mode.

15. The system of claim 13, wherein the particular mode defines a number of bits per cell.

16. The system of claim 13, wherein the particular programming algorithm is selected from a group including a course programming algorithm, a fine programming algorithm, and a superfine programming algorithm.

17. The system of claim 13, wherein the first command is not placed in a command queue for execution.

18. The system of claim 13, wherein execution of the first command does not include a data transfer phase.

19. The system of claim 13, wherein the second command is a read operation.

20. The system of claim 13, wherein the second command is a write operation.