GATE STACK OPTIMIZATION FOR WIDE AND NARROW NANOSHEET TRANSISTOR DEVICES

• US 20200035563A1
• Filed: 07/27/2018
• Published: 01/30/2020
• Est. Priority Date: 07/27/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Zhang, Jingyun, Ando, Takashi, Lee, Choonghyun
• Granted Patent: US 10,643,899 B2
• Time in Patent Office: Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method of forming a nanosheet device is provided. The method includes forming a plurality of narrow nanosheets on a first region of a substrate, and forming a plurality of wide nanosheets on a second region of the substrate. The method further includes forming an interfacial layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes depositing a gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes depositing a dummy gate layer on the gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets. The method further includes forming a dummy cover layer on the dummy gate layer on the plurality of narrow nanosheets and the plurality of wide nanosheets.

Claims

1. A method of forming a nanosheet device, comprising:

forming a plurality of narrow nanosheets on a first region of a substrate;

forming a plurality of wide nanosheets on a second region of the substrate;

forming an interfacial layer on the plurality of narrow nanosheets and the plurality of wide nanosheets;

depositing a gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets;

depositing a dummy gate layer on the gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets; and

forming a dummy cover layer on the dummy gate layer on the plurality of narrow nanosheets and the plurality of wide nanosheets.

2. The method of claim 1, wherein adjacent narrow nanosheets of the plurality of narrow nanosheets on the first region of a substrate and the adjacent wide nanosheets of the plurality of wide nanosheets on the second region of a substrate are separated by a distance, D₁, in a range of about 5.5 nm to about 17.5 nm.

3. The method of claim 1, wherein the dummy cover layer is formed on the dummy gate layer by a non-confoiiiial deposition.

4. The method of claim 3, wherein foaming the dummy cover layer by a non-confoiival deposition creates void spaces between adjacent narrow nanosheets of the plurality of narrow nanosheets and void spaces between adjacent wide nanosheets of the plurality of wide nanosheets.

5. The method of claim 1, further comprising forming a blocking layer on the dummy cover layer on the plurality of narrow nanosheets on the first region of a substrate and the plurality of wide nanosheets on the second region of a substrate.

6. The method of claim 5, further comprising heat treating the blocking layer, the plurality of narrow nanosheets on the first region of a substrate, and the plurality of wide nanosheets on the second region of a substrate.

7. The method of claim 6, wherein the heat treatment is a furnace anneal at a temperature in a range of about 850°

C. to about 1100°

C.

8. The method of claim 7, wherein the heat treatment is conducted for a duration of about 100 nanoseconds to about 1 millisecond.

9. The method of claim 6, further comprising removing the blocking layer, the dummy cover layer, and the dummy gate layer.

10. The method of claim 9, further comprising forming a conductive gate layer on the gate dielectric layer on the plurality of narrow nanosheets on the first region of a substrate and the plurality of wide nanosheets on the second region of a substrate.

11. A method of forming a nanosheet device, comprising:

forming a plurality of narrow nanosheets on a first region of a substrate;

forming a plurality of wide nanosheets on a second region of the substrate;

forming an interfacial layer on each of the plurality of narrow nanosheets and the plurality of wide nanosheets, wherein the interfacial layer is a semiconductor oxide;

depositing a gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets;

depositing a dummy gate layer on the gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets; and

forming a dummy cover layer on the dummy gate layer on the plurality of narrow nanosheets and the plurality of wide nanosheets, wherein the dummy cover layer is the same material as the dummy gate layer.

12. The method of claim 11, wherein the dummy cover layer and dummy gate layer are selected from the group of metal nitrides consisting of titanium nitride (TiN), titanium aluminum nitride (TiAlN), hafnium nitride (HfN), hafnium silicon nitride (HfSiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN), and combinations thereof.

13. The method of claim 11, further comprising forming a blocking layer on the dummy cover layer on the plurality of narrow nanosheets on the first region of a substrate and the plurality of wide nanosheets on the second region of a substrate.

14. The method of claim 13, wherein the blocking layer is made of a material that prevents oxygen (O₂) from penetrating to the dummy cover layer.

15. The method of claim 13, further comprising heat treating the blocking layer, the plurality of narrow nanosheets on the first region of a substrate, and the plurality of wide nanosheets on the second region of a substrate at a temperature in a range of about 900°

C. to about 1010°

C.

16. A nanosheet device, comprising:

a plurality of narrow nanosheets on a first region of a substrate;

a plurality of wide nanosheets on a second region of the substrate, wherein adjacent narrow nanosheets of the plurality of narrow nanosheets on the first region of a substrate and the adjacent wide nanosheets of the plurality of wide nanosheets on the second region of a substrate are separated by a distance, D₁, in a range of about 5.5 nm to about 17.5 nm;

an interfacial layer on the plurality of narrow nanosheets and the plurality of wide nanosheets;

a gate dielectric layer on the plurality of narrow nanosheets and the plurality of wide nanosheets; and

a conductive gate layer on the gate dielectric layer.

17. The nanosheet device of claim 16, wherein the plurality of narrow nanosheets have a width of about 10 nanometers (nm) to about 25 nm.

18. The nanosheet device of claim 17, wherein the plurality of wide nanosheets have a width of about 60 nm to about 120 nm.

19. The nanosheet device of claim 18, further comprising a raised mesa below the plurality of narrow nanosheets, wherein the plurality of narrow nanosheets forms at least one vertical stack, and a raised mesa below the plurality of wide nanosheets, wherein the plurality of wide nanosheets forms at least another vertical stack.

20. The nanosheet device of claim 19, further comprising an isolation region formed in the substrate between the one vertical stack and the other vertical stack.