WRITE CYCLE EXECUTION BASED ON DATA COMPARISON

• US 20200058334A1
• Filed: 09/16/2019
• Published: 02/20/2020
• Est. Priority Date: 08/14/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Frederiksen, Jeffrey
• Granted Patent: US 10,672,440 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0882 Page mode
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 2207/2263 Write conditionally, e.g. only if new data and old data differ
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Aspects of the present disclosure include a memory sub-system configured to reduce latency and power consumption during a read-write cycle. The memory system comprises a first memory component and a processing device operatively coupled to the first memory component. The processing device is configured to receive a request to write a first sequence of data bits from a first data block of a second memory component to memory media of the first memory component. In response to receiving the request, the processing device reads a second sequence of data bits from a second data block stored in the memory media of the first memory component, and compares the first sequence of data bits with the second sequence of data bits. The processing device determines whether to execute a write cycle, at the first memory component, to write the first sequence of data bits from the first data block to the memory media of the first memory component based on a result of comparing the first sequence of data bits with the second sequence of data bits.

Claims

1. A system comprising:

a first memory component; and

a processing device, operatively coupled to the first memory component to determine whether to execute a write cycle, at the first memory component, to write a first sequence of data bits from a second memory component to the first memory component based on a comparison of the first sequence of data bits with a second sequence of data bits stored by the second memory component.

2. The system of claim 1, wherein the operations further comprise:

foregoing execution of the write cycle, at the first memory component, in response to determining that the first and second sequences of data bits are identical.

3. The system of claim 1, wherein the operations further comprise:

executing the write cycle in response to identifying at least one difference between the first and second sequences of data bits.

4. The system of claim 3, wherein the write cycle comprises:

writing at least one data bit from the first sequence of data bits to the first memory component.

5. The system of claim 4, wherein the writing of the at least one data bit from the first sequence of data bits to the first memory component includes writing over at least one stored data bit in the second data block, the at least one stored data bit corresponding to the at least one difference between the first and second sequences of data bits.

6. The system of claim 1, wherein:

each data bit in the first sequence of data bits has a corresponding data bit in the second sequence of data bits; and

the comparing of the first sequence of data bits with the second sequence of data bits comprises comparing each data bit in the first sequence of data bits with the corresponding data bit in the second sequence of data bits.

7. The system of claim 1, wherein:

the first memory component is configured as a secondary memory component; and

the second memory component is configured as a primary memory component.

8. The system of claim 1, wherein:

the first memory component includes a non-volatile memory component; and

the second memory component includes a volatile memory component.

9. The system of claim 1, wherein the processing device is further to:

receive a request to write the first sequence of data bits from a first data block of the second memory component to the first memory component;

in response to receiving the request, reading the second sequence of data bits from a second data block stored in at the first memory component; and

comparing the first sequence of data bits with the second sequence of data bits.

15. The system of claim 1, wherein:

each data bit in the cached data has a corresponding data bit in the persisted data; and

the comparing of the cached data and the persisted data comprises comparing each data bit in the cached data with the corresponding data bit in the persisted data.

10. A system comprising:

a non-volatile memory component comprising a persisted data block storing persisted data;

a volatile memory component comprising a cached data block stored cached data;

and

a memory sub-system controller, operatively coupled to the non-volatile memory component, configured to perform operations comprising;

receiving a request to write the cached data from the cached data block of the volatile memory component to the non-volatile memory component; and

determining whether to execute a write cycle, at the non-volatile memory component, to write the cached data from the cached data block to the non-volatile memory component based on a comparison of the cached data with the persisted data.

11. The system of claim 10, wherein the operations further comprise:

foregoing execution of the write cycle, at the non-volatile memory component, in response to determining that the cached data and the persisted data are identical.

12. The system of claim 10, wherein the operations further comprise:

executing the write cycle in response to identifying at least one difference between the cached data and the persisted data.

13. The system of claim 12, wherein the write cycle comprises:

writing at least a portion of the cached data to the non-volatile memory component.

14. The system of claim 13, wherein the writing of at least the portion of the cached data to the non-volatile memory component includes writing over at least one stored data bit in the persisted data block, the at least one stored data bit corresponding to the at least one difference between the between the cached data and the persisted data.

16. A method comprising:

receiving, at a media controller operatively coupled to a non-volatile memory component and a volatile memory component, a request to write cached data from a cached data block of the volatile memory component to the non-volatile memory component; and

determining, by the media controller, whether to execute a write cycle, at the non-volatile memory component, to write the cached data from the cached data block to the non-volatile memory component based on a comparison of the cached data with a persisted data stored by the non-volatile memory component.

17. The method of claim 16, wherein the operations further comprise:

foregoing execution of the write cycle, at the non-volatile memory component, in response to determining that the cached data and the persisted data are identical.

18. The method of claim 16, wherein the operations further comprise:

executing the write cycle in response to identifying at least one difference between the cached data and the persisted data.

19. The method of claim 18, wherein the write cycle comprises:

writing at least a portion of the cached data to the non-volatile memory component.

20. The method of claim 19, wherein the writing of at least the portion of the cached data to the non-volatile memory component includes writing over at least one stored data bit in the persisted data block, the at least one stored data bit corresponding to the at least one difference between the between the cached data and the persisted data.