METHODS AND APPARATUS FOR CONTROL OF A JOINTLY SHARED MEMORY-MAPPED REGION

• US 20200065244A1
• Filed: 08/24/2018
• Published: 02/27/2020
• Est. Priority Date: 08/24/2018
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Sanghi, Karan, Garg, Saurabh, McElrath, Jason
• Granted Patent: US 10,846,224 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes
• CPC Class Codes: G06F 9/546 Message passing systems or structures, e.g. queues

Abstract

Methods and apparatus for using and controlling a jointly shared memory-mapped region between multiple processors in a pass-through manner. Existing data pipe input/output (I/O) techniques for mobile device operation enable high speed data transfers, decoupled independent operation of processors, reduced software complexity, reduced power consumption, etc. However, legacy functions and capabilities may only receive marginal benefits from data pipe I/O operation, and in some cases, may even suffer adverse effects from e.g., processing overhead and/or context switching. The present disclosure is directed to dynamically isolating and reaping back a jointly shared memory space for data transfer in a “pass through” manner which does not require kernel space intervention. More directly, a jointly shared region of host memory is accessible to both the peripheral client and the host client in user space.

Claims

1. A method for using a jointly shared memory between a first processor and a second processor, comprising:

opening a pass-through application;

mapping a jointly shared memory space for the pass-through application;

accessing the jointly shared memory space via the pass-through application; and

closing the pass-through application.

2. The method of claim 1, wherein opening the pass-through application comprises opening a user space application.

3. The method of claim 2, wherein:

the accessing of the jointly shared memory space comprises writing data to the jointly shared memory space; and

the method further comprises;

causing a peer application to read the written data from the jointly shared memory space.

4. The method of claim 2, wherein:

the mapping of the jointly shared memory space for the pass-through application comprises assigning a physical address location within a memory device to a virtual address for a memory-mapped input/output (I/O).

5. The method of claim 2, wherein the user space application can read and write to a physical address location of the jointly shared memory space without context switching to a kernel space communication stack.

6. The method of claim 1, wherein the accessing of the jointly shared memory space comprises queueing a plurality of accesses of the jointly shared memory space.

7. The method of claim 6, further comprising:

responsive to closing the pass-through application, flushing any outstanding accesses of the plurality of queued accesses.

8. The method of claim 1, wherein the accessing of the jointly shared memory space comprises writing an entry within a ring buffer.

9. The method of claim 1, further comprising:

changing a parameter of the jointly shared memory space based on a non-coordinated message.

10. An apparatus, comprising:

a host processor coupled to a peripheral processor; and

a non-transitory computer readable medium comprising one or more instructions which when executed by the host processor, cause the host processor to;

manage one or more data pipe transactions via a kernel space communication stack within a shared memory;

map a jointly shared memory space within the shared memory, the jointly shared memory space accessible via a memory-mapped input/output (I/O) in user space; and

access the jointly shared memory space via a pass-through application.

11. The apparatus of claim 10, wherein the host processor comprises an application processor and the pass-through application comprises a streaming audio application.

12. The apparatus of claim 10, wherein the one or more data pipe transactions are managed via a transfer ring (TR) of an inter-processor communication (IPC) driver.

13. The apparatus of claim 12, wherein the jointly shared memory space within the shared memory is reserved from a memory space associated with the IPC driver.

14. The apparatus of claim 12, wherein the jointly shared memory space within the shared memory is allocated from unallocated memory.

15. An apparatus, comprising:

a peripheral processor coupled to a host processor; and

a non-transitory computer readable medium comprising one or more instructions which when executed by the peripheral processor, cause the peripheral processor to;

receive a memory map message identifying a jointly shared memory space within a shared memory;

access the jointly shared memory space via a pass-through application; and

transmit a non-coordinated control message to signal an event associated with the jointly shared memory space.

16. The apparatus of claim 15, wherein the peripheral processor comprises a media processor and the pass-through application comprises a streaming audio application that uses a memory-mapped input/output (I/O) to access the jointly shared memory space.

17. The apparatus of claim 15, wherein the non-coordinated control message comprises a completion descriptor (CD) that does not correspond to a transfer descriptor (TD).

18. The apparatus of claim 15, wherein the jointly shared memory space comprises a circular buffer within user space.

19. The apparatus of claim 18, wherein the non-coordinated control message is transmitted via a kernel space communication stack.

20. The apparatus of claim 19, wherein the event associated with the jointly shared memory space comprises a wrap of the circular buffer.