INTEGRATED CIRCUIT PACKAGE STRUCTURE AND PACKAGE METHOD

• US 20200083131A1
• Filed: 06/14/2019
• Published: 03/12/2020
• Est. Priority Date: 09/12/2018
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: WANG, Zhidong, LAN, Ronghua
• Granted Patent: US 10,910,288 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/293 Organic, e.g. plastic
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26

Abstract

An integrated circuit package structure and a package method. The integrated circuit package structure includes: a semiconductor chip, an encapsulation layer covering the semiconductor chip, the encapsulation layer including a first encapsulation layer and a second encapsulation layer alternately stacked, a sum of a number of the first encapsulation layer and a number of the second encapsulation layer being at least 3; wherein a thermal expansion coefficient of one of the first encapsulation layer and the second encapsulation layer is positive, and a thermal expansion coefficient of the other of the first encapsulation layer and the second encapsulation layer is negative.

Claims

1. An integrated circuit package structure comprising:

a semiconductor chip; and

an encapsulation layer covering the semiconductor chip, the encapsulation layer comprising a first encapsulation layer and a second encapsulation layer alternately stacked, a sum of a number of the first encapsulation layer and a number of the second encapsulation layer being at least 3,

wherein a thermal expansion coefficient of one of the first encapsulation layer and the second encapsulation layer is positive, and a thermal expansion coefficient of the other of the first encapsulation layer and the second encapsulation layer is negative.

2. The integrated circuit package structure according to claim 1, wherein an absolute value of the thermal expansion coefficient of the first encapsulation layer is equal to an absolute value of the thermal expansion coefficient of the second encapsulation layer.

3. The integrated circuit package structure according to claim 2, wherein the absolute value of the thermal expansion coefficient of the first encapsulation layer is 8-13 ppm/°

C., and the absolute value of the thermal expansion coefficient of the second encapsulation layer is 8-13 ppm/°

C.

4. The integrated circuit package structure according to claim 1, wherein one of the first encapsulation layer and the second encapsulation layer has a composite material of an epoxy resin and a first inorganic compound, the other of the first encapsulation layer and the second encapsulating layer has a composite material of an epoxy resin and a second inorganic compound, the first inorganic compound and the second inorganic compound have a negative thermal expansion coefficient, and an absolute value of the thermal expansion coefficient of the first inorganic compound is less than an absolute value of the thermal expansion coefficient of the second inorganic compound.

5. The integrated circuit package structure according to claim 1, further comprising:

a redistribution layer and a solder ball, wherein the redistribution layer comprises a first side and a second side opposite to the first side, the semiconductor chip and the encapsulation layer are located at the first side, the solder ball is located at the second side.

6. The integrated circuit package structure according to claim 5, wherein a side of the semiconductor chip facing the redistribution layer comprises a solder pad, the encapsulation layer coats a surface of the semiconductor chip other than a surface of the solder pad.

7. The integrated circuit package structure according to claim 2, wherein a thickness of the first encapsulation layer is equal to a thickness of the second encapsulation layer.

8. The integrated circuit package structure according to claim 1, wherein an absolute value of the thermal expansion coefficient of the first encapsulation layer is greater than an absolute value of the thermal expansion coefficient of the second encapsulation layer, and a thickness of the first encapsulation layer is less than a thickness of the second encapsulation layer;

or, an absolute value of the thermal expansion coefficient of the first encapsulation layer is less than an absolute value of the thermal expansion coefficient of the second encapsulation layer, and a thickness of the first encapsulation layer is greater than a thickness of the second encapsulation layer.

9. A package method of an integrated circuit, comprising:

attaching a semiconductor chip on a package carrier;

forming a first encapsulation layer and a second encapsulation layer alternately stacked on the package carrier to obtain an encapsulation layer, the encapsulation layer covering the semiconductor chip, one of the first encapsulation layer and the second encapsulation layer having a positive thermal expansion coefficient, and the other of the first encapsulation layer and the second encapsulation layer having a negative thermal expansion coefficient.

10. The package method according to claim 9, wherein a thermal expansion coefficient of the package carrier is 0-11 ppm/°

C.

11. The package method according to claim 9, wherein forming the first encapsulation layer and the second encapsulation layer alternately stacked on the package carrier, comprises:

forming at least one first encapsulation material layer and at least one second encapsulation material layer alternately stacked on the package carrier sequentially;

heating and curing the first encapsulation material layer and the second encapsulation material layer, to obtain the first encapsulation layer and the second encapsulation layer alternately stacked.

12. The package method according to claim 9, further comprising:

after forming the first encapsulation layer and the second encapsulation layer alternately stacked on the package carrier, removing the package carrier;

forming a redistribution layer on an exposed side of the semiconductor chip, and forming a solder ball on a side of the redistribution layer facing away from the semiconductor chip.

13. The package method according to claim 12, further comprising:

after forming the solder ball on the side of the redistribution layer facing away from the semiconductor chip, cutting the encapsulation layer to obtain a plurality of integrated circuit package structures.

14. The package method according to claim 9, wherein an absolute value of the thermal expansion coefficient of the first encapsulation layer is equal to an absolute value of the thermal expansion coefficient of the second encapsulation layer.

15. The package method according to claim 14, wherein the absolute value of the thermal expansion coefficient of the first encapsulation layer is 8-13 ppm/°

C., and the absolute value of the thermal expansion coefficient of the second encapsulation layer is 8-13 ppm/°

C.

16. The package method according to claim 9, wherein one of the first encapsulation layer and the second encapsulation layer has a composite material of an epoxy resin and a first inorganic compound, the other of the first encapsulation layer and the second encapsulating layer has a composite material of an epoxy resin and a second inorganic compound, the first inorganic compound and the second inorganic compound have a negative thermal expansion coefficient, and an absolute value of the thermal expansion coefficient of the first inorganic compound is less than an absolute value of the thermal expansion coefficient of the second inorganic compound.

17. The package method according to claim 12, wherein a side of the semiconductor chip facing the redistribution layer comprises a solder pad, the encapsulation layer coats a surface of the semiconductor chip other than a surface of the solder pad.

18. The package method according to claim 14, wherein a thickness of the first encapsulation layer is equal to a thickness of the second encapsulation layer.

19. The package method according to claim 9, wherein an absolute value of the thermal expansion coefficient of the first encapsulation layer is greater than an absolute value of the thermal expansion coefficient of the second encapsulation layer, and a thickness of the first encapsulation layer is less than a thickness of the second encapsulation layer;

or, an absolute value of the thermal expansion coefficient of the first encapsulation layer is less than an absolute value of the thermal expansion coefficient of the second encapsulation layer, and a thickness of the first encapsulation layer is greater than a thickness of the second encapsulation layer.