INTEGRATED CIRCUIT PACKAGE STRUCTURE AND PACKAGE METHOD

  • US 20200083131A1
  • Filed: 06/14/2019
  • Published: 03/12/2020
  • Est. Priority Date: 09/12/2018
  • Status: Active Grant
First Claim
Patent Images

1. An integrated circuit package structure comprising:

  • a semiconductor chip; and

    an encapsulation layer covering the semiconductor chip, the encapsulation layer comprising a first encapsulation layer and a second encapsulation layer alternately stacked, a sum of a number of the first encapsulation layer and a number of the second encapsulation layer being at least 3,wherein a thermal expansion coefficient of one of the first encapsulation layer and the second encapsulation layer is positive, and a thermal expansion coefficient of the other of the first encapsulation layer and the second encapsulation layer is negative.

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