SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
First Claim
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1. A method of manufacturing a semiconductor device, comprising:
- forming a stacked structure including alternately stacked semiconductor layers and sacrificial layers;
forming a sacrificial gate structure over the stacked structure;
forming a dielectric layer over the sacrificial gate structure;
removing the sacrificial gate structure, thereby forming a gate space;
removing the sacrificial layers in the gate space, thereby releasing the semiconductor layers; and
forming a gate structure wrapping around the semiconductor layers,wherein the semiconductor layers are made of an oxide semiconductor material.
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Abstract
A semiconductor device includes a power switch circuit and a logic circuit. The semiconductor device includes a first dielectric layer and a thin film transistor (TFT) formed on the first dielectric layer. The TFT includes a semiconductor nano-sheet, a gate dielectric layer wrapping around a channel region of the semiconductor nano-sheet, and a gate electrode layer formed on the gate dielectric layer. The semiconductor nano-sheet is made of an oxide semiconductor material.
7 Citations
20 Claims
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1. A method of manufacturing a semiconductor device, comprising:
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forming a stacked structure including alternately stacked semiconductor layers and sacrificial layers; forming a sacrificial gate structure over the stacked structure; forming a dielectric layer over the sacrificial gate structure; removing the sacrificial gate structure, thereby forming a gate space; removing the sacrificial layers in the gate space, thereby releasing the semiconductor layers; and forming a gate structure wrapping around the semiconductor layers, wherein the semiconductor layers are made of an oxide semiconductor material. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of manufacturing a semiconductor device, comprising:
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forming a fin structure including alternately stacked semiconductor layers and sacrificial layers over a first dielectric layer; forming a sacrificial gate structure over the fin structure; forming gate sidewall spacers on opposing side faces of the sacrificial gate structure; forming a second dielectric layer over the sacrificial gate structure and the fin structure; removing the sacrificial gate structure, thereby forming a gate space; removing the sacrificial layers in the gate space, thereby releasing channel regions of the semiconductor layers; forming a gate structure wrapping around the channel regions of the semiconductor layers; forming a third dielectric layer; forming a contact opening in the third dielectric layer and the second dielectric layer; removing the sacrificial layers in the contact opening, thereby releasing source/drain regions of the semiconductor layers; and forming a source/drain contact wrapping around the source/drain regions of the semiconductor layers, wherein the semiconductor layers are made of an oxide semiconductor material. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A semiconductor device including a power switch circuit and a logic circuit, the power switch circuit comprising:
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a first dielectric layer; a thin film transistor (TFT) formed on the first dielectric layer, wherein; the TFT includes; semiconductor nano-sheets vertically arranged; a gate dielectric layer wrapping around a channel region of each of the semiconductor nano-sheets; a gate electrode layer formed on the gate dielectric layer, wherein the semiconductor nano-sheets are made of an oxide semiconductor material. - View Dependent Claims (17, 18, 19, 20)
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Specification