INTERCALATED METAL/DIELECTRIC STRUCTURE FOR NONVOLATILE MEMORY DEVICES
First Claim
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1. An integrated chip including a memory device, the memory device comprising:
- a bottom electrode disposed over a semiconductor substrate;
an upper electrode disposed over the bottom electrode; and
an intercalated metal/dielectric structure sandwiched between the bottom electrode and the upper electrode, the intercalated metal/dielectric structure comprising a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.
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Abstract
Some embodiments relate to an integrated chip including a memory device. The memory device includes a bottom electrode disposed over a semiconductor substrate. An upper electrode is disposed over the bottom electrode. An intercalated metal/dielectric structure is sandwiched between the bottom electrode and the upper electrode. The intercalated metal/dielectric structure comprises a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric lower, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.
6 Citations
20 Claims
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1. An integrated chip including a memory device, the memory device comprising:
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a bottom electrode disposed over a semiconductor substrate; an upper electrode disposed over the bottom electrode; and an intercalated metal/dielectric structure sandwiched between the bottom electrode and the upper electrode, the intercalated metal/dielectric structure comprising a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An integrated chip, comprising:
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an interconnect structure including a lower metal layer and an upper metal layer which are separated from one another by a first inter-level dielectric (ILD) layer; a bottom electrode disposed over the lower metal layer; a top electrode disposed over the bottom electrode, the top electrode residing below the upper metal layer; and a plurality of metal layers and a plurality of dielectric layers stacked in alternating fashion over one another and sandwiched between the top electrode and the bottom electrode. - View Dependent Claims (11, 12, 13, 14)
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15. A method, comprising:
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forming a lower interconnect structure within a first inter-level dielectric (ILD) layer over a substrate; forming an intercalated metal/dielectric structure over the lower interconnect structure, the intercalated metal/dielectric structure comprising a lower dielectric layer over the lower interconnect structure, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer; and forming an upper electrode over the intercalated metal/dielectric structure. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification