Positive Logic Switch with Selectable DC Blocking Circuit

• US 20200153425A1
• Filed: 11/13/2019
• Published: 05/14/2020
• Est. Priority Date: 03/28/2018
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Inventors: Ranta, Tero Tapio, Willard, Simon Edward
• Granted Patent: US 10,862,473 B2
• Time in Patent Office: Days
• CPC Class Codes: H03K 17/0412 by measures taken in the control circuit
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 17/6874 in a symmetrical configuration
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 2017/066 Maximizing the OFF-resistance instead of minimizing the ON-resistance
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its V_GS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero V_GS type, or a mix of positive-logic and zero V_GS type FETs with end-cap FETs of the zero V_GS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

Claims

1. A stack of FET switches, at least one FET switch configured so as to not require a negative power supply to effectively turn the FET switch OFF, series-coupled on at least one end to an end-cap FET that effectively turns OFF when the V_GS of such end-cap FET is essentially zero volts.

2. The invention of claim 1, further including a second end-cap FET that effectively turns OFF when the V_GS of the second end-cap FET is essentially zero volts, series-coupled to a second end of the stack of FET switches.

3. The invention of claim 1, further including at least one additional FET that effectively turns OFF when the V_GS of such FET is essentially zero volts, series coupled to the stack of FET switches.

4. The invention of claim 1, wherein each end-cap FET substantially blocks DC current flow when in an OFF state and provides a resistive signal path when in an ON state.

5. The invention of claim 1, further including at least one capacitor coupled between the source and the drain of a corresponding end-cap FET.

6. The invention of claim 1, further including a gate bias resistor ladder including a plurality of series-coupled resistors configured to be coupled to a gate bias voltage, wherein each resistor is coupled to the respective gates of corresponding adjacent FET switches.

7. The invention of claim 6, wherein the stack of FET switches includes a radio frequency port, and further including an AC coupling gate module coupled between an end of the gate bias resistor ladder and the radio frequency port.

8. The invention of claim 7, wherein the AC coupling gate module includes one of a capacitor or a capacitor series coupled to a resistor.

9. The invention of claim 1, further including a body charge control resistor ladder including a plurality of resistors configured to be coupled to a body bias voltage, wherein each resistor is coupled to the body of at least one corresponding FET switch.

10. The invention of claim 9, wherein the stack of FET switches includes a radio frequency port, and further including an AC coupling body module coupled between an end of the body charge control resistor ladder and the radio frequency port.

11. The invention of claim 10, wherein the AC coupling body module includes one of a capacitor or a capacitor series coupled to a resistor.

12. The invention of claim 1, further including a drain-source resistor ladder including a plurality of series-coupled resistors configured to be coupled to a drain-source bias voltage, wherein each resistor is coupled to the respective drains and sources of corresponding adjacent FET switches.

13. The invention of claim 1, wherein at least one FET switch and/or end-cap FET is an ACS FET.

14. The invention of claim 1, further including a negative gate bias voltage supply coupled to the gates of the end-cap FETs.

15. A series-shunt switch circuit including:

(a) a series FET switch stack having an input port and an output port; and

(b) a shunt FET switch stack coupled to the output port of the series FET switch stack, and configured to be coupled to a reference potential;

wherein at least one of the series FET switch stack and the shunt FET switch stack includes at least one series-coupled end-cap FET that effectively turns OFF when the V_GS of such end-cap FET is essentially zero volts.

16. The invention of claim 15, wherein at least one of the series FET switch stack and the shunt FET switch stack further includes a respective second end-cap FET that effectively turns OFF when the V_GS of the second end-cap FET is essentially zero volts, series-coupled to a second end of the respective FET switch stack.

17. The invention of claim 15, wherein each end-cap FET substantially blocks DC current flow when in an OFF state and provides a resistive signal path when in an ON state.

18. A series-shunt switch circuit including:

(a) a series FET switch stack having an input port and an output port; and

(b) a shunt FET switch stack coupled to the output port of the series FET switch stack, and configured to be coupled to a reference potential;

wherein at least one of the series FET switch stack and the shunt FET switch stack includes at least one series-coupled positive-logic FET, series-coupled to at least one end-cap FET that effectively turns OFF when the V_GS of such end-cap FET is essentially zero volts.

19. The invention of claim 18, wherein at least one of the series FET switch stack and the shunt FET switch stack further includes a respective second end-cap FET that effectively turns OFF when the V_GS of the second end-cap FET is essentially zero volts, series-coupled to a second end of the respective FET switch stack.

20. The invention of claim 18, wherein each end-cap FET substantially blocks DC current flow when in an OFF state and provides a resistive signal path when in an ON state.