DUAL-GATE THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE
First Claim
1. A dual-gate thin film transistor, comprising:
- a base substrate;
a first gate disposed on the base substrate;
a first gate insulating layer disposed on the first gate, the first gate insulating layer comprising a first via hole exposing a portion of the first gate;
an active layer disposed on the first gate insulating layer, the active layer and the first gate at least partially overlapping with each other in a direction perpendicular to the base substrate;
a second gate insulating layer disposed on the active layer;
a first electrode and a second electrode, which are disposed in contact with the active layer;
a second gate disposed on the second gate insulating layer, the second gate and the active layer at least partially overlapping with each other in a direction perpendicular to the base substrate, and the second gate, the first electrode and the second electrode formed in a same layer; and
a connection electrode electrically connected with the second gate and electrically connected with the first gate through the first via hole.
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Accused Products
Abstract
A dual-gate thin film transistor, a manufacturing method thereof, an array substrate and a display device are provided. The dual-gate thin film transistor includes: a base substrate and a first gate, a first gate insulating layer, an active layer, a second gate insulating layer, a first electrode, a second electrode, a second gate and a connection electrode, formed on the base substrate. The second gate, the first electrode and the second electrode are formed on the same level. The first gate insulating layer includes a first via hole exposing a portion of the first gate, and the connection electrode is electrically connected with the second gate and is electrically connected with the first gate through the first via hole.
4 Citations
20 Claims
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1. A dual-gate thin film transistor, comprising:
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a base substrate; a first gate disposed on the base substrate; a first gate insulating layer disposed on the first gate, the first gate insulating layer comprising a first via hole exposing a portion of the first gate; an active layer disposed on the first gate insulating layer, the active layer and the first gate at least partially overlapping with each other in a direction perpendicular to the base substrate; a second gate insulating layer disposed on the active layer; a first electrode and a second electrode, which are disposed in contact with the active layer; a second gate disposed on the second gate insulating layer, the second gate and the active layer at least partially overlapping with each other in a direction perpendicular to the base substrate, and the second gate, the first electrode and the second electrode formed in a same layer; and a connection electrode electrically connected with the second gate and electrically connected with the first gate through the first via hole. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 15, 20)
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12. A method for manufacturing a dual-gate thin film transistor, comprising:
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providing a base substrate; forming a first gate on the base substrate; forming a first gate insulating layer on the first gate; forming an active layer on the first gate insulating layer, the active layer partially overlapping the first gate in a direction perpendicular to the base substrate; forming a second gate insulating layer on the active layer; forming a second gate, a first electrode and a second electrode through one conductive layer, wherein the second gate is disposed on the second gate insulating layer and partially overlaps the active layer in a direction perpendicular to the base substrate, and both the first electrode and the second electrode are in contact with the active layer; and forming a connection electrode, which is electrically connected with the second gate and is electrically connected with the first gate. - View Dependent Claims (13, 14, 16, 17, 18, 19)
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Specification