Power Sourcing Equipment, and Method and Apparatus for Power Over Ethernet

• US 20200295956A1
• Filed: 03/31/2020
• Published: 09/17/2020
• Est. Priority Date: 10/13/2016
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: He, Ling
• Granted Patent: US 11,025,443 B2
• Time in Patent Office: Days
• CPC Class Codes: G05B 7/02 electric
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H04L 12/10 Current supply arrangements
• CPC Class Codes: H04L 12/12 Arrangements for remote connection or disconnection of substations or of equipment thereof
• CPC Class Codes: H04L 12/40045 Details regarding the feeding of energy to the node from the bus

Abstract

An Ethernet power sourcing equipment (P SE), and a method and an apparatus for power over Ethernet (PoE), where the Ethernet PSE includes a PSE chip, a master control processor, a power supplying port, and a preprocessor. The preprocessor is configured to determine whether the master control processor starts upon power-on, control the PSE chip to detect whether the power supplying port is connected to a valid powered device (PD) when the master control processor starts upon power-on, and control, according to a preset rule, the PSE chip to power on the valid PD when the power supplying port is connected to the valid PD. Hence, the Ethernet PSE has abundant management functions and can quickly power on a PD.

Claims

1. A power sourcing equipment (P SE), comprising:

a PSE chip;

a master control processor coupled to the PSE chip;

a power supplying port coupled to the PSE chip; and

a preprocessor coupled to the master control processor and the PSE chip, wherein the preprocessor is configured to, without waiting for starting a main program by the master control processor, the following processes;

determine whether the master control processor starts upon power-on;

control the PSE chip to detect whether the power supplying port is connected to a valid powered device (PD) when the master control processor starts upon power-on; and

control, according to a preset rule, the PSE chip to power on the valid PD when the power supplying port is connected to the valid PD.

2. The PSE of claim 1, wherein the master control processor is configured to:

determine whether the PSE chip has supplied power to a PD;

obtain state information of the PSE chip when the PSE chip has supplied power to the PD;

initialize the PSE chip when the PSE chip has not supplied power to the PD; and

complete system configuration according to a pre-stored configuration rule.

3. The PSE of claim 1, wherein when controlling the PSE chip to power on the valid PD, the preprocessor is further configured to:

obtain total output power of a power supply for PDs;

obtain an agreed power of each PD;

determine a to-be-powered-on PD according to the total output power and the agreed power of each PD; and

control the PSE chip to power on the to-be-powered-on PD.

4. The PSE of claim 1, wherein the preprocessor and the master control processor are configured to run in a master control chip of the PSE, and wherein the preprocessor is further configured to run before the master control processor loads the main program.

5. The PSE of claim 1, wherein the preprocessor and the master control processor are configured to run in a master control chip of the PSE, and wherein the preprocessor is further configured to run before the master control processor skips to the main program.

6. The PSE of claim 1, wherein the master control processor is configured to run in a master control chip of the PSE, wherein the preprocessor is configured to run in a microcontroller independent of the master control chip, and wherein the microcontroller is connected to a power supply and the PSE chip.

7. The PSE of claim 1, further comprising a volatile memory, wherein the volatile memory is disposed in the master control processor, wherein the master control processor is configured to obtain a detection result by detecting whether data in the volatile memory is no longer stored, and wherein the preprocessor is further configured to determine whether the master control processor starts upon power-on based on the detection result.

8. The PSE of claim 1, further comprising a volatile memory, wherein the volatile memory is coupled to the master control processor, wherein the master control processor is configured to obtain a detection result by detecting whether data in the volatile memory is no longer stored, and wherein the preprocessor is further configured to determine whether the master control processor starts upon power-on based on the detection result.

9. The PSE of claim 1, further comprising a volatile memory, wherein the volatile memory is disposed in the master control processor, and wherein the preprocessor is configured to:

obtain a detection result by determining whether data in the volatile memory is no longer stored; and

determine whether the master control processor starts upon power-on based on the detection result.

10. The PSE of claim 1, further comprising a volatile memory, wherein the volatile memory is coupled to the master control processor, and wherein the preprocessor is configured to:

obtain a detection result by determining whether data in the volatile memory is no longer stored; and

determine whether the master control processor starts upon power-on based on the detection result.

11. The PSE of claim 1, wherein the master control processor is configured to calculate a logical result according to a clock signal, a reset signal, and a related state parameter of the master control processor using a preset logical algorithm, and wherein the preprocessor is further configured to:

obtain the logical result from the master control processor; and

determine, according to the logical result, whether the master control processor starts upon power-on.

12. The PSE of claim 1, wherein the preprocessor is further configured to:

calculate a logical result according to a clock signal, a reset signal, and a related state parameter of the master control processor using a preset logical algorithm; and

determine, according to the logical result, whether the master control processor starts upon power-on.

13. A method for power over Ethernet (PoE) used in an Ethernet power sourcing equipment (PSE), comprising:

determining, by a preprocessor, whether a master control processor starts upon power-on, wherein the Ethernet PSE comprises the preprocessor, a PSE chip, and a power supplying port;

controlling, by the preprocessor and without waiting for starting a main program by the master control processor, the PSE chip to detect whether the power supplying port is connected to a valid powered device (PD) when the master control processor starts upon power-on; and

controlling, by the preprocessor according to a preset rule, the PSE chip to power on the valid PD when the power supplying port is connected to the valid PD.

14. The method of claim 13, further comprising:

determining, by the master control processor, whether the PSE chip has supplied power to a PD;

obtaining, by the master control processor, state information of the PSE chip when the PSE chip has supplied power to the PD;

initializing, by the master control processor, the PSE chip when the PSE chip has not supplied power to the PD; and

completing, by the master control processor, system configuration according to a pre- stored configuration rule.

15. The method of claim 13, wherein powering on the valid PD comprises:

obtaining, by the preprocessor, total output power of a power supply for PDs;

obtaining, by the preprocessor, an agreed power of each PD;

determining, by the preprocessor, a to-be-powered-on PD according to the total output power and the agreed power of each PD; and

controlling, by the preprocessor, the PSE chip to power on the to-be-powered-on PD.

16. The method of claim 13, wherein determining whether the master control processor starts upon power-on comprises:

detecting, by the preprocessor, whether data in a volatile memory is no longer stored, wherein the volatile memory is disposed in the master control processor; and

determining, by the preprocessor, whether the master control processor starts upon power-on based on the data in the volatile memory no longer being stored.

17. The method of claim 13, wherein determining whether the master control processor starts upon power-on comprises:

detecting, by the preprocessor, whether data in a volatile memory is no longer stored, wherein the volatile memory is coupled to the master control processor; and

determining, by the preprocessor, whether the master control processor starts upon power-on based on the data in the volatile memory no longer being stored.

18. The method of claim 13, wherein determining whether the master control processor starts upon power-on comprises:

calculating, by the preprocessor, a logical result according to a clock signal, a reset signal, and a related state parameter of the master control processor using a preset logical algorithm; and

determining, by the preprocessor, according to the logical result, whether the master control processor starts upon power-on.

19. A computer program product comprising computer-executable instructions for storage on a non-transitory computer-readable medium that, when executed by a processor, cause a preprocessor of an Ethernet power sourcing equipment (PSE) to:

determine whether a master control processor starts upon power-on, wherein the Ethernet PSE comprises the preprocessor, a PSE chip, and a power supplying port;

control, without waiting for starting a main program by the master control processor, the PSE chip to detect whether the power supplying port is connected to a valid powered device (PD) when the master control processor starts upon power-on; and

control, according to a preset rule, the PSE chip to power on the valid PD when the power supplying port is connected to the valid PD.

20. The computer program product of claim 19, wherein the instructions further cause the preprocessor to:

obtain total output power of a power supply for PDs;

obtain an agreed power of each PD;

determine a to-be-powered-on PD according to the total output power and the agreed power of each PD; and

control the PSE chip to power on the to-be-powered-on PD.