REAL-TIME DIGITAL SPECTRUM ANALYZER UTILIZING THE FAST FOURIER TRANSFORM

• US 3,573,446 A
• Filed: 06/06/1967
• Issued: 04/06/1971
• Est. Priority Date: 06/06/1967
• Status: Expired due to Term

• Current Assignee: Glenn D. Bergland
• Original Assignee: Glenn D. Bergland
• Inventors: Bergland, Glenn D.
• Application Number:
  US04/643,902
• Time in Patent Office: 1,400 Days
• US Class Current: 708/404
• CPC Class Codes: G06F 17/142 Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm

Abstract

A digital signal processing system for computing the finite discrete Fourier transform coefficients from a number (N) of digitized samples of an input signal in real time. The signal being analyzed is sampled a predetermined number of times over a given interval, and this number of samples is expressed as the product of two integers, N r1. r2. An array of delay registers is arranged in the form of a matrix having r1columns and r2 rows. The delay registers are controlled so that the contents may be transferred either in a column shift mode or in a row shift mode. While shifting the contents of the array in the row shift mode, the system computes an intermediate set of spectrum estimates which are stored in the array. From this intermediate set, the final coefficients are generated while shifting the contents of the array in its column shift mode.

Claims

1. A digital spectrum analyzer for computing the finite discrete Fourier transform coefficients from a number (N) of digitized samples, represented by A(k), of an input signal comprising:

an array of delay registers forming a matrix having r1 columns and r2 rows;

row shift means for transferring the contents of said delay registers in a row shift mode wherein the contents of a delay register are transferred to the adjacent register in a higher order column along the same row, the contents of the delay register in the highest order columns being transferred to the delay register in the next higher order row and of the lowest order column;

means operative independently of said row shift means for transferring the contents of said delay registers in a column shift mode wherein the contents of said delay registers are transferred along the same column to an adjacent delay register of higher order row, the contents of the delay registers in the highest order row being transferred to the delay register in the next higher order column and lowest order row, the output of the delay register in the highest order column and highest order row defining the output of said array;

multiplier means receiving said input signals for multiplying said signal by a predetermined value of a weighting factor;

adder means for adding the output of said array and for storing the resultant in the delay register of lowest order column and lowest order row; and

control means for operating on each of said A(k) input signals, said operation including transferring said input signal to said multiplier means wherein it is multiplied by said weighting factor signal, shifting the contents of said array in said row shift mode, transferring the output of said multiplier means and the output of said array to said adder means wherein they are added, and storing the output of said adder means in the first delay register of said array, said control means operating on each of said A(k) input signals a total of r1 times, whereby intermediate estimates of said Fourier coefficients are stored in said delay registers.

2. The apparatus of claim 1 wherein said control means is operative after said r1 operations to transfer the output of said array to the input of said multiplier means, and further comprising first register means receiving the output signals of said adder means;

means for coupling the output signals of said first register means to one input of said adder means;

means for rendering said weighting factor signal generator in a second mode of operation for supplying signals to the other input of said complex multiplier; and

second control means for rendering operative said multiplier means to multiply the contents of said weighing factor signal generator with the output signals of said array, for adding in said adder means the contents of said multiplier means with the contents of said first register means and for storing the results in said first register, and for coupling said array output to said array input; and

means for actuating said array in said column shift mode and for repeating the operation of said second control means a total of r2 times thereby computing each of N of the complex spectral coefficients which may be fed to an output while operating said array in said column shift mode.

3. The apparatus of claim 2 wherein said weighting factor signal generator comprises:

means for storing a constant signal representative of a value Wr ;

means for storing a constant signal representative of a value W1, second multiplier means;

second and third register means;

means for selectively coupling the output of said second multiplier means to either of said last-named registers;

switching means for selectively coupling the output signal of said second register to said first multiplier means or to said second multiplier means;

means for selectively coupling said constant signals to said second multiplier means;

means for setting said third register to a signal value WN r ;

means for setting said second register to a signal value W0;

means for coupling the output of said third register and the output of said signal Wr to said second multiplier means and for storing the product in said third register;

means for coupling the output of said second register to the input of said first multiplier means as one of said weighting factor signals;

means for selectively coupling the contents of said second and third registers to the input of said second multiplier means and for storing the product in said second register; and

further control means for repeating said last-named operation a total of N times thereby supplying said first N values of said weighting factor signal.

4. The apparatus of claim 3 further comprising means for repeating the operation therein a total of r1 times thereby supplying a number N.r1 of values of said weighting factor required for said first mode of operation.

5. The apparatus of claim 4 wherein said means for operating said Weighting factor signal generator in a second mode of operation comprises means for resetting said third register to a value of WN 1;

means for resetting said second register to a value W0;

means for coupling the contents of said third register and the contents of said W1 to said second multiplier; and

means for storing the product in said third register;

means for selectively coupling the contents of said second register to said first multiplier;

means whereby the contents of said second and third registers are multiplied and the product stored in said second register;

means for repeating said last-named steps a total of r2 times; and

means for repeating said second mode of operation a total of N times thereby supplying a total of N.r2 values of said weighting factor in said second mode of operation.