MEASURING CORRELATION, AMPLITUDE PROBABILITY AND PROBABILITY DENSITY DISTRIBUTIONS, AND SIGNAL RESPONSE AVERAGING

• US 3,626,168 A
• Filed: 07/07/1969
• Issued: 12/07/1971
• Est. Priority Date: 07/07/1969
• Status: Expired due to Term

• Current Assignee: Keith H. Norsworthy
• Original Assignee: Keith H. Norsworthy
• Inventors: Norsworthy, Keith H.
• Primary Examiner(s): Morrison, Malcolm A.
• Assistant Examiner(s): Gruber, Felix D.
• Application Number:
  US04/839,340
• Time in Patent Office: 883 Days
• Field of Search: 235/181,152,150.52 324/77R,77G
• US Class Current: 702/57
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: G06F 17/18 for evaluating statistical data , e.g. average values, frequency distributions, probability functions, regression analysis forecasting specially adapted for a specific administrative, business or logistic context G06Q10/04
• CPC Class Codes: G06G 7/1928 for forming correlation integrals; for forming convolution integrals G06G7/195, G06G7/1907 and G06G7/1914 take precedence

Abstract

An online real-time instrument for measurement of auto and cross correlation, amplitude probability distribution and amplitude probability density distributions of random analog signals and for measurement of average signal response characteristics. A scanning averager utilized in all the measurements includes capabilities for adapting its time constant to differing clock rates and for selecting its time constant at will for longer and shorter averaging times and for controlling the range of selfadaptivity. The correlation circuitry includes special timing controls for both basic and high frequency modes and combines analog and digital circuit design. The latter is accompanied by provision of a synchronized pseudo-random noise source to assure uniform probability density distribution for the full scale range of the input signal. Conservation of circuitry is achieved through use of the same circuitry for the different measurements of which the instrument is capable. Special logic is included for enhancement of amplitude probability distribution measurements.

Claims

1. A system for analysis of first and second electrical signals, comprising:

a. first sampling means for providing samples of the first signal;

b. second sampling means for providing quantized digital samples of the second signal;

c. a shift register coupled to the second sampling means for receiving and storing successively derived values of said quantized digital samples, said register having Q-stages into which said samples are shifted sequentially, where Q is an integer;

d. multiplying means having Q multiplication channels, each channel being coupled to the first sampling means and to one of the shift register stages for multiplying said quantized digital samples stored therein by samples from said first sampling means;

e. averaging means including Q sets of separate signal averagers, each set being response to one of said multiplication channels, respectively, and each consisting of a plurality P of said averagers, where the product P(Q) equals the number of desired output values;

f. scanning means for intermittently connecting each of said Q multiplication channels successively to each of the P averagers in the set of averagers responsive thereto; and

g. timing control apparatus including;

1. first control means coupled to the first sampling means to effect sampling of the first signal at intervals N Delta Tau , where N is an integer equal to unity, P1 or P1;

2. second control means coupled to second sampling means to effect sampling of the second signal at intervals M Delta Tau , where M is an integer equal to P;

3. third control means coupled to the shift register to effect shifting of second signal samples at intervals R Delta Tau , where R is an integer equal to one of the integers N and M, and 4. fourth control means coupled to the scanning means for effecting connections of each multiplication channel to the separate averagers in the set responsive thereto, sequentially at intervals N Delta Tau .

2. second control means coupled to the second sampling means, said second control means further including means stepping said reference signal generating means from one value of said pseudorandom digital code to the next in synchronism with the sampling of said second signal.

3. third control means coupled to the shift register to effect shifting of second signal samples at intervals R Delta Tau , where R is an integer equal to one of the integers N and M, and

4. The system defined in claim 3 wherein said timing control apparatus includes:

a. variable frequency clock means for providing a basic timing waveform;

b. said first control means and said fourth control means include a ring counter having M+1 output stages successively energized in response to said basic timing waveform;

c. said first altering means of said mode selection means utilizes said M output stages thereof for said first mode of operation and utilizing said M+1 output stages for said second mode of operation;

d. said first control means and said fourth control means each including means coupled to the first output stage of said ring counter.

5. The system defined in claim 4 wherein said timing control apparatus further includes:

a. a second ring counter within said second and third control means having M output stages successively energized in response to an applied timing waveform;

b. said third altering means of said mode selection means further including a switch coupled to the first output stage of the first mentioned ring counter and to said clock means for selectively applying to the input of said second counter the waveform provided at the first output stage of said first mentioned ring counter for first mode of operation and applying said basic timing waveform thereto for said second mode of operation; and

c. said second and third control means include means coupled to the waveform provided at the first output stage of said second ring counter.

6. The system defined in claim 1 wherein said timing control apparatus includes:

a. first means altering said second control means to effect sampling of the second signal at intervals (N-1) Delta Tau or (N+1) Delta Tau , whereby M N-1 or N+1 and N>

1;

b. second means altering said third control means to effect shifting of said shift register at intervals N Delta Tau , whereby R+N;

c. said third control means further includes an auxiliary control for shifting said register one extra shift for each Nth shift thereof; and

, d. each of said Q sets of averagers includes a plurality N-1 or N+1 of said averagers, whereby P N-1 or N+1.

7. The analyzer defined in claim 1 wherein said second sampling means includes:

a. a digital comparator for providing said quantized digital samples of the second signal with respect to a reference signal, b. reference signal generating means for generating a psuedoransom digital code having a uniform probability distribution over the full scale range of the second signal to be applied to said analyzer, said generating means being responsive to said second control means for stepping from one value of said code to the next in synchronism with sampling of said second signal, and c. means for connecting said generating means to said comparator.

8. The analyzer defined in claim 1, including:

a. a digital comparator for providing said quantized digital samples of said second signal with respect to reference level, b. a variable length shift register interposed between said comparator and the first-mentioned shift register for providing a selectable amount of precomputation delay prior to multiplication of said first and second signal samples, and c. means coupling said variable length shift register to said second control means foR shifting said quantized digital samples of said second signal at intervals M Delta Tau .

9. The analyzer defined in claim 1, further including:

a. means for generating a ramp signal, b. means for comparing the second signal with said ramp signal and providing said quantized digital samples indicating whether the second signal is greater or less than said ramp signal, c. means for rendering said shift register ineffective and for applying signals corresponding to said quantized digital samples to said multiplication means output channels, d. fifth control means coupled to the scanning means to effect intermittent connections of said separate averagers to said output channels in sequence whereby the averagers in the first set are connected sequentially, followed by those in the next set sequentially, through all sets, and e. sixth control means coupled to said ramp signal generating means to effect one repetition of said ramp signal in synchronism with each complete sequence of connections by said scanning means.

10. The analyzer defined in claim 9, further including:

a. means for providing a constant-level reference signal Delta V and adding it to said ramp signal to form a sum signal;

b. second comparing means for comparing said second signal to said sum signal and providing quantized signal values indicating whether the second signal is greater or less than said sum signal;

c. an OR circuit responsive to both of said comparing means for providing said quantized digital samples indicating whether said second signal is within Delta V of said ramp signal; and

d. means for preventing application of said quantized digital samples from the first comparing means to said multiplication means output channels and applying thereto said quantized digital samples provided by said Or circuit.

11. The analyzer defined in claim 9 further including weighting means coupled to said timing control apparatus and responsive to said quantized digital samples provided by said comparing means for preventing application to said averagers of a predetermined fraction of those samples provided by said comparing means which indicate that the second signal is greater than or less than said ramp signal.

12. The analyzer defined in claim 1 further including a. means coupled with said shift register for providing equal signal values thereto whereby said multiplying means output channels provide signal values proportional to said samples of the first input signal;

b. fifth control means coupled to the scanning means to effect connections of said averagers to said multiplying means output channels in a complete sequence whereby the averagers in the first set are connected sequentially, followed by those in the next set sequentially, and so on through all sets;

c. an auxiliary input for receiving a trigger signal;

d. means responsive to the auxiliary input and coupled to said fifth control means for effecting one complete scanning sequence following occurrence of a trigger signal at said auxiliary input and preventing another scan until occurrence of another trigger signal, and further including;

13. The analyzer defined in claim 1 wherein each of said averagers comprises an input and an output;

an averaging filter circuit consisting of a resistance coupled between the input and output, and an output capacitor coupled between the output and ground; and

an input capacitor coupled between the input and ground and having a capacitance value much smaller than the output capacitor.

14. The analyzer defined in claim 13 wherein said timing control apparatus includes means for varying the rate of sampling of said signaLs and the rate of multiplying the samples thereof.

15. The analyzer defined in claim 13 wherein said timing control apparatus includes means for varying the dwell time during which each of said separate averagers is connected to said multiplying means output channels by said scanning means.

16. A system for analysis of first and second electrical signals, comprising:

a. A first sampling means for providing samples of the first signal, b. a second sampling means for providing digital samples of the second signal, said second sampling means including a digital comparator for quantizing the second signal with respect to a reference level to provide said digital samples, a reference signal generating means for generating a pseudorandom digital code having a uniform probability distribution over the full scale range of the second signal to the applied to said system, and means for connecting said reference signal generating means to said digital comparator;

c. a multiplying means having one or more multiplication channels being coupled to said first and second sampling means for multiplying said digital samples by said samples from said first sampling means;

d. an averaging means including a plurality of signal averagers coupled to each of said multiplication channels; and

e. a timing control apparatus, including