• US 3,654,610 A
  • Filed: 09/28/1970
  • Issued: 04/04/1972
  • Est. Priority Date: 09/28/1970
  • Status: Expired due to Term
First Claim
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1. A memory system having an array of a predetermined number of storage cells, each for storing a single bit of binary information, arranged in orthogonal lines, the lines each having binary addresses, comprising:

  • at least one redundant line of storage cells and one or more defective lines in the same direction as the redundant line, the contained cells of said redundant lines not being required to make up said predetermined number of storage cells and the number of redundant lines being at least equal to the number of defective lines;

    a code converter permanently connected to electrically convert the binary addresses for each of the lines of the system to combinatorial addresses, each combinatorial address being associated with a line of the array, the maximum number of combinatorial addresses to which the binary addresses of all the lines may be converted being at least one more than the maximum number of binary addresses of all the lines in the same direction, there being no binary address associated with the additional combinatorial addresses; and

    means selectively connecting said code converter to said array of storage cells, and selective connection providing that said additional combinatorial addresses are associated with said defective lines, and the combinatorial addresses with which the binary addresses of the defective lines would normally be associated are associated with the redundant lines.

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