CIRCUIT TESTER

• US 3,673,397 A
• Filed: 10/02/1970
• Issued: 06/27/1972
• Est. Priority Date: 10/02/1970
• Status: Expired due to Term

• Current Assignee: Link Flight Simulation Corporation Kirkwood Industrial Park Binghamton NY 13902-1237
• Original Assignee: Bruce M. Schaefer
• Inventors: Schaefer, Bruce M.
• Primary Examiner(s): Botz, Eugene G.
• Assistant Examiner(s): Dildine, Jr., R. Stephen
• Application Number:
  US05/077,478
• Time in Patent Office: 634 Days
• Field of Search: 324/73R,73PC 235/153
• US Class Current: 714/736
• CPC Class Codes: G01R 31/3193 with comparison between actual response and known fault free response receiver details G01R31/31924

Abstract

The disclosed embodiment of the present invention is an automatic circuit tester for providing stimuli to, sensing responses from, and sensing the condition of individual input and output terminals of the circuit under test. Identical circuit means are provided for each input and output terminal of the circuit under test, and each includes a storage device for storing a prediction of the expected response of the stimulus to be applied to a corresponding input terminal of the circuit under test. Each of the circuit means also includes a logic circuit for comparing the prediction of the expected response and producing a '"'"''"'"''"'"''"'"'fail'"'"''"'"''"'"''"'"' signal upon the occurrence of non-coincidence therebetween. Each of the circuit means are automatically provided with data corresponding to the prediction of the expected response or the stimulus to be applied to the circuit under test from a programmable record such as a data processing card. In addition, each circuit means is capable of responding to or providing stimulus in the proper form to the corresponding terminal in accordance with the type of logic employed in the circuit under test. This is accomplished by employing translators for converting input and output signals to appropriate signals which are compatible with the type of logic employed in the circuit means and in the circuit under test. Each circuit means is programmed by programable data processing cards and the information programmed on such cards is strobed by appropriate timing and encoding circuits into a corresponding one of the circuit means.

Claims

1. A testing circuit having a terminal disposed for connection to a unit under test wherein a stimulus is supplied to the unit under test in response to one state of the testing circuit and receives a response from the unit under test in response to another state of the testing circuit, comprising:

a. means for storing a signal in the form of one of two digital levels;

b. programmable storage means having two states;

c. a gate having one input connected to said signal storing means and another input connected to said storage means and an output disposed for connection to said terminal, whereby the output provides the stimulus to the unit under test; and

d. comparing means having one input connected to said terminal and the output of said gate, and another input connected to said signal storing means and providing an output in response to non-coincidence between said signal and the response from the unit under test, whereby such output is an indication of a failure.

2. programmable storage means having two states;

3. A system as defined in claim 2, wherein said converting means includes a controllable conduction element having a conductive path in two directions therethrough.

4. comparing means having one input connected to one of said terminals and the output of said gate, and another input connected to said signal storing means and providing an output in response to non-coincidence between said signal and the response from the output terminal of the digital circuit, whereby such output is an indication of a failure;

b. means for reading a programmed record to provide data corresponding to the information contained thereon; and

c. means responsive to said reading means for selectively energizing each of said circuit means.

5. A system for testing a digital circuit having a plurality of input and output terminals wherein the system provides stimuli to the input terminals and receives responses from the output terminals of the digital circuit in the form of two digital levels, comprising:

a. a plurality of circuit means each disposed for connection to a respective terminal of such a digital circuit, each of said circuit means including,