COMBINED MODEM AND VOCODER PIPELINE PROCESSOR

• US 3,706,929 A
• Filed: 01/04/1971
• Issued: 12/19/1972
• Est. Priority Date: 01/04/1971
• Status: Expired due to Term

• Current Assignee: John L. Robinson, Robert F. Munnich
• Original Assignee: John L. Robinson, Robert F. Munnich
• Inventors: Robinson, John L., Munnich, Robert F.
• Primary Examiner(s): Mayer, Albert J.
• Application Number:
  US05/103,503
• Time in Patent Office: 715 Days
• Field of Search: 179/1SA,15.55 324/77R,77A,77B 325/30,38B,38R,15 178/67 340/148,152
• US Class Current: 375/216
• CPC Class Codes: H04B 1/66 for reducing bandwidth of signals; for improving efficiency of transmission H04B1/68 takes precedence
• CPC Class Codes: H04L 27/205 in which the data are represented by the change in phase of the carrier
• CPC Class Codes: H04L 27/2338 using sampling H04L27/2331 - H04L27/2335 take precedence

Abstract

A digital pipeline processing system for implementing both vocoder and data modem functions. The pipeline capability is provided by three circulating memories and two associated arithmetic units. The first circulating memory and its arithmetic unit implement the functions of vocoder spectrum analysis modem modulation and modem demodulation. The second circulating memory and its arithmetic unit implement the functions of vocoder pitch extraction, vocoder parameter filtering, and vocoder speech synthesis. The third circulating memory is used for temporary storage of data while computations are carried out by the other circulating memories and their arithmetic units. The processing system also comprises a control unit which provides timing and gating signals for control of the remainder of the processor, an impulse response synthesizer which provides sinusoids used in speech synthesis, encoding and decoding circuitry for formating data, and a plurality of read-only memories for permanent storage of functions required by the processor.

Claims

1. A digital apparatus having a first operating mode wherein said apparatus is responsive to a first input signal representative of a first speech wave in the time domain, and a second alternative operating mode wherein said apparatus is responsive to a second input signal (i) representative of the power spectrum and the pitch frequency of a second speech wave and (ii) comprising a plurality of differentially coherent phase shift keyed tones, said apparatus comprising:

first means for a. computing from said first input signal the power spectrum of said first speech wave, b. generating a binary representation of a modulated carrier comprising a plurality of differentially coherent phase shift keyed tones, said modulation bearing the power spectrum and the pitch frequency of said first speech wave, and c. recovering from said second input signal the power spectrum and the pitch frequency of said second speech wave, said First means comprising;

first and second memories, a first adder having an output connected to the input of said first memory, a first multiplier, means for coupling the outputs of said first multiplier to an input of said first adder, first and second read-only memories, means for coupling the output of said first read-only memory to said input of said first adder, means for coupling the output of said second read-only memory to an input of said first multiplier, means for connecting the output of said first memory to said input of said first adder and to inputs of said first multiplier and to the input of said second read-only memory and to the input of said second memory, and means for connecting the output of said second memory to the input of said second memory and to an input of said first multiplier; and

second means for a. computing the pitch frequency of said first speech wave, b. supplying said pitch frequency of said first speech wave to said first means, and c. generating from the power spectrum and pitch frequency recovered by said first means a binary representation of said second speech wave in the time domain, said second means comprising;

a third memory, a second adder having its output connected to the input of said third memory, a second multiplier having its output connected to an input of said second adder, means for connecting the output of said third memory to an input of said second multiplier and to an input of said second adder, means for connecting the output of said second memory to an input of said second multiplier, means, having an input coupled to the output of said third memory, for synthesizing the impulse response of a plurality of filters each responsive to pass a different one of said plurality of tones, means for connecting the output of said impulse response synthesizer means to an input of said second multiplier, means for generating a plurality of noiselike signals each having a center frequency corresponding to a different one of said plurality of tones, and means for connecting the output of said noise generator means to an input of said second adder.

2. A digital apparatus according to claim 1, wherein said means for coupling the outputs of said first multiplier to said first adder comprises first and second data switches, means coupling one output of said first multiplier to an input of said first data switch, means coupling another output of said first multiplier to an input of said second data switch, a third adder, means coupling the respective outputs of said first and second data switches to respective inputs of said third adder, and means coupling the output of said third adder to an input of said first adder.

3. A digital apparatus according to claim 2, further comprising pitch selection means and voicing decision means, means coupling the output of said second adder means to the input of said pitch selection means, means coupling the respective outputs of said pitch selection means and said third adder to respective inputs of said voicing decision means;

vocoder data processor means and modem data processor means, means coupling the output of said voicing decision means to said first data switch and to an input of said vocoder data processor means, means connecting an output of said modem data processor means to an input of said vocoder data processor means, means connecting an output of said vocoder data processor means to an input of said modem data processor means, first accumulator means having an input coupled to an output of said first multiplier and an output coupled to an input of said modem data processor means, means coupling an output of said modem data processor means to the input of said first read-only memory, said means for coupling the output of said first read-only memory to said first adder comprising said first data switch and said third adder;

a third read-only memory having an input coupled to the output of said third adder, encoder means having an input coupled to the oUtput of said third read-only memory and having an output coupled to an input of said vocoder data processor, decoder means having an input coupled to an output of said vocoder data processor, linear interpolator means having an input coupled to the output of said decoder means and an input coupled to the output of said third memory and an output coupled to an input of said third memory;

a third data switch having one input coupled to the output of said second read-only and having another input coupled to the output of said second multiplier means, second accumulator means having an input coupled to the output of said third data switch;

first analog-to-digital converter means alternatively responsive to said first input signal and said second input signal, a fourth data switch having respective inputs coupled to the outputs of said impulse response synthesizer means and said first analog-to-digital converter and having an output coupled to an input of said second multiplier, a fifth data switch having respective inputs coupled to said output of said first analog-to-digital converter, said output of said second read-only memory, said output of said second memory and said output of said third memory and having an output coupled to an input of said second multiplier;

a sixth data switch having respective inputs coupled to said output of said first analog-to-digital converter, said output of said first memory and said output of said second memory, and having an output coupled to said input of said second memory;

a seventh data switch having respective inputs coupled to said first analog-to-digital converter, the output of said first memory, the output of said second memory, and that output of said first multiplier which is coupled to an input of said second data switch, and having an output coupled to one input of said first multiplier; and

an eighth data switch having respective inputs coupled to the output of said second read-only memory and the output of said first memory, and having an output coupled to another input of said first multiplier.

4. A digital apparatus according to claim 3, wherein said first read-only memory stores values of a weighting function, and channel address increments, said second read-only memory stores values of a sine wave, and said third read-only memory stores values of logarithms, and wherein said apparatus also comprises a second digital-to-analog converter having its input coupled to the output of said second accumulator means.