GYRATOR EMPLOYING FIELD EFFECT TRANSISTORS

• US 3,715,693 A
• Filed: 03/20/1972
• Issued: 02/06/1973
• Est. Priority Date: 03/20/1972
• Status: Expired due to Term

• Current Assignee: Erwin S. Hochmair
• Original Assignee: Erwin S. Hochmair
• Inventors: Hochmair, Erwin S.
• Primary Examiner(s): Gensler, Paul L.
• Application Number:
  US05/236,281
• Time in Patent Office: 323 Days
• Field of Search: 333/8R,8T 307/304 330/12,35,3D
• US Class Current: 333/215
• CPC Class Codes: H03H 11/42 Gyrators used in frequency selective networks H03H11/08

Abstract

A gyrator circuit of the conventional configuration of two amplifiers in a circular loop, one producing zero phase shift and the other producing 180* phase reversal. All active elements are MOS field effect transistors. Each amplifier comprises a differential amplifier configuration with current limiting transistor, followed by an output transistor in cascode configuration, and two load transistors of opposite conductivity type from the other transistors. A voltage divider control circuit comprises a series string of transistors with a central, voltage input to provide control, with locations on the amplifiers receiving reference voltages by connection to appropriate points on the divider. The circuit produces excellent response and is well suited for fabrication by integrated circuits.

Claims

1. A gyrator circuit comprising a first, differential amplifier stage comprising at least two active elements having control inputs, at least one of said active elements producing an output of said first amplifier and being a field effect transistor, one of said control inputs of said first amplifier being connected to a first terminal, the other of said control inputs of said first amplifier being connected to a source of reference potential, at least one field effect transistor connected to the output of said field effect transistor of said first amplifier in a first cascode configuration;

a second, differential amplifier stage comprising at least two active elements having control inputs, at least one of said active elements producing an output of said second amplifier and being a field effect transistor, one of said control inputs of said second amplifier being connected to a second terminal and to the output of said first cascode configuration with said output being substantially the same phase as the input of said first amplifier, the other of said control inputs of said second amplifier being connected to a source of reference potential, at least one field effect transistor connected to the output of said field effect transistor of said second amplifier in a second cascode configuration, the output of said second cascode configuration being connected to said first terminal with said output being substantially the reversed phase of the input of said second amplifier.

2. The gyrator circuit as in claim 1 also including a voltage divider circuit having an input terminal for a control voltage, said reference potentials being provided by connection to said voltage divider circuit.

3. The gyrator circuit as in claim 2 in which said voltage divider circuit comprises at least three field effect transistors connected in series between two, different potential sources, said input terminal is connected to the gate of the central of said series connected transistors, and said reference potentials are provided by connection directly to different, individual ones of the other two terminals of said central transistor.

4. The gyrator circuit as in claim 1 in which said field effect transistors of said first amplifier and said first cascode configuration are of one conductivity type and said field effect transistors of said second amplifier and said second cascode configuration are of the opposite conductivity type.

5. The gyrator circuit as in claim 4 also including a voltage divider circuit having an input terminal for a control voltage, said reference potentials being provided by connection to said voltage divider circuit.

6. The gyrator circuit as in claim 5 in which said voltage divider circuit comprises at least three field effect transistors connected in series between two, different potential sources, said input terminal is connected to the gate of the central of said series connected transistors, said reference potentials are provided by connection directly to different, individual ones of the other two terminals of said central transisTor, and the transistor of said series connected transistors connected between each said reference-potential connection and an end of said voltage divider circuit being of the same conductivity type as the said transistors of the amplifier stage and cascode configuration to which the reference potential is connected.

7. The gyrator circuit as in claim 4 in which said output of said first cascode configuration is connected in drain-to-drain series to at least one field effect transistor of opposite conductivity type from the transistors of said first amplifier and said first cascode configuration and in which said output of said second cascode configuration is connected in drain-to-drain series to at least one field effect transistor of opposite conductivity type from the transistors of said second amplifier and said second cascode configuration.

8. The gyrator circuit as in claim 7 also including a voltage divider circuit having an input terminal for a control voltage, said reference potentials being provided by connection to said voltage divider circuit.

9. The gyrator circuit as in claim 8 in which said voltage divider circuit comprises at least three field effect transistors connected in series between two, different potential sources, said input terminal is connected to the gate of the central of said series connected transistors, said reference potentials are provided by connection directly to different, individual ones of the other two terminals of said central transistor, the transistor of said series connected transistors connected between each said reference-potential connection and an end of said voltage divider circuit being of the same conductivity type as the said transistors of the amplifier stage and cascode configuration to which the reference potential is connected, the gate of the transistor in said first cascode configuration connected to the transistor of opposite conductivity type and the gate of that transistor of opposite conductivity type are connected to said reference potential connected to said second amplifier, and the gate of the transistor of said second cascode configuration connected to the transistor of opposite conductivity type and the gate of that transistor of opposite conductivity type are connected to said reference potential connected to said first amplifier.

10. The gyrator circuit as in claim 7 in which said first and said second differential amplifier stages each comprise at least four field effect transistors, two of said transistors in each said amplifier being connected respectively to said terminal and to said reference potential and being connected together source-to-source through a resistor, each of said two transistors being connected source-to-drain through individual of the other of said four transistors to a potential source.

11. The gyrator circuit as in claim 10 in which the output from said first cascode configuration is connected to one of said two transistors in said second amplifier which are connected respectively to said terminal and to said reference potential and in which the output from said second cascode configuration is connected to the transistor in said first amplifier which corresponds to the transistor in said second amplifier other than the one of said two transistors to which said output from said first cascode configuration is connected to said second amplifier.

12. The gyrator circuit as in claim 9 in which said first and said second differential amplifier stages each comprise at least four field effect transistors of the same conductivity type, two of said transistors in each said amplifier being connected respectively to said terminal and to said reference potential and being connected together source-to-source through a resistor, each of said two transistors being connected source-to-drain through individual of the other of said four transistors to a potential source and in which the gates of said transistors in said voltage divider circuit connected to the central transistor arE connected to the nearest terminal of said central transistor, and said voltage divider circuit also includes field effect transistors connected in source-to-drain series between each said transistor connected to the central transistor and one of said two potential sources, each being of the same conductivity type as the said transistor connected to the central transistor to which it is connected, the gate of each being connected to the gates of the two said other transistors which are connected to a potential source of a said amplifier comprising transistors of that same conductivity type and to the location of connection of the two transistors of that same conductivity type in said voltage divider circuit.

13. The gyrator circuit as in claim 12 in which the output from said first cascode configuration is connected to one of said two transistors in said second amplifier which are connected respectively to said terminal and to said reference potential and in which the output from said second cascode configuration is connected to the transistor in said first amplifier which corresponds to the transistor in said second amplifier other than the one of said two transistors to which said output from said first cascode configuration is connected to said second amplifier.

14. The gyrator circuit as in claim 10 in which each said transistor of opposite conductivity type connected to each said cascode configuration is connected in source-to-drain series with another field effect transistor of the same conductivity type.

15. The gyrator circuit as in claim 12 in which each said transistor of opposite conductivity type connected to each said cascode configuration is connected in source-to-drain series with another field effect transistor of the same conductivity type, and in which the gate of each said another transistor is connected to the location of connection of the two transistors which are both of that same conductivity type connected to the central transistor in said voltage divider circuit.

16. The gyrator circuit as in claim 15 in which the output from said first cascode configuration is connected to one of said two transistors in said second amplifier which are connected respectively to said terminal and to said reference potential and in which the output from said second cascode configuration is connected to the transistor in said first amplifier which corresponds to the transistor in said second amplifier other than the one of said two transistors to which said output from said first cascode configuration is connected to said second amplifier.

17. The gyrator circuit as in claim 1 in which at least one of said terminals is connected in parallel with a circuit branch which provides a differential response not referenced to ground to an input at that terminal, the differential response being connected as the differential input to the said differential amplifier stage to which that terminal is connected.

18. The gyrator circuit as in claim 4 in which at least one of said terminals is connected in parallel with a circuit branch which provides a differential response not referenced to ground to an input at that terminal, the differential response being connected as the differential input to the said differential amplifier stage to which that terminal is connected.

19. The gyrator circuit as in claim 7 in which at least one of said terminals is connected in parallel with a circuit branch which provides a differential response not referenced to ground to an input at that terminal, the differential response being connected as the differential input to the said differential amplifier stage to which that terminal is connected.

20. The gyrator circuit as in claim 7 also including a voltage divider circuit having an input terminal for a control voltage, said voltage divider circuit comprising at least three field effect transistors connected in series between two, different potential sources, said input terminal being connected to the gate of the central of said serieS connected transistors, the gate of the transistor in said first cascode configuration connected to the transistor of opposite conductivity type and the gate of that transistor of opposite conductivity type being connected to one of the two other terminals of said central transistor, the gate of the transistor of said second cascode configuration connected to the transistor of opposite conductivity type and the gate of that transistor of opposite conductivity type being connected to the other of said two other terminals of said central transistor, the transistor of said series connected transistors connected between the nearest of said two other terminals of said central transistor and an end of said voltage divider circuit being of the opposite conductivity type to that of the transistor of the cascode configuration to which that said nearest terminal of the central transistor is connected, and in which at least one of said terminals is connected in parallel with a circuit branch which provides a differential response not referenced to ground to an input at that terminal, the differential response being connected as the differential input to the said differential amplifier stage to which that terminal is connected.

21. The gyrator circuit as in claim 10 in which at least one of said terminals is connected in parallel with a circuit branch which provides a differential response not referenced to ground to an input at that terminal, the differential response being connected as the differential input to the said differential amplifier stage to which that terminal is connected.

22. The gyrator circuit as in claim 11 in which at least one of said terminals is connected in parallel with a circuit branch which provides a differential response not referenced to ground to an input at that terminal, the differential response being connected as the differential input to the said differential amplifier stage to which that terminal is connected.

23. The gyrator circuit as in claim 20 in which said first and said second differential amplifier stages each comprise at least four field effect transistors of the same conductivity type, two of said transistors in each said amplifier being connected respectively to said terminal and to said reference potential and being connected together source-to-source through a resistor, each of said two transistors being connected source-to-drain through individual of the other of said four transistors to a potential source and in which the gates of said transistors in said voltage divider circuit connected to the central transistor are connected to the nearest terminal of said central transistor, and said voltage divider circuit also includes field effect transistors connected in source-to-drain series between each said transistor connected to the central transistor and one of said two potential sources, each being of the same conductivity type as the said transistor connected to the central transistor to which it is connected, the gate of each being connected to the gates of the two said other transistors which are connected to a potential source of a said amplifier comprising transistors of that same conductivity type and to the location of connection of the two transistors of that same conductivity type in said voltage divider circuit, and in which at least one of said terminals is connected in parallel with a circuit branch which provides a differential response not referenced to ground to an input at that terminal, the differential response being connected as the differential input to the said differential amplifier stage to which that terminal is connected.

24. The gyrator circuit as in claim 23 in which the output from said first cascode configuration is connected to one of said two transistors in said second amplifier which are connected respectively to said terminal and to said reference potential and in which the output from said second cascode configuration is connected to the transistor in said first amplifier which corresponds tO the transistor in said second amplifier other than the one of said two transistors to which said output from said first cascode configuration is connected to said second amplifier.

25. The gyrator circuit as in claim 14 in which at least one of said terminals is connected in parallel with a circuit branch which provides a differential response not referenced to ground to an input at that terminal, the differential response being connected as the differential input to the said differential amplifier stage to which that terminal is connected.

26. The gyrator circuit as in claim 23 in which each said transistor of opposite conductivity type connected to each said cascode configuration is connected in source-to-drain series with another field effect transistor of the same conductivity type, and in which the gate of each said another transistor is connected to the location of connection of the two transistors which are both of that same conductivity type connected to the central transistor in said voltage divider circuit.

27. The gyrator circuit as in claim 26 in which the output from said first cascode configuration is connected to one of said two transistors in said second amplifier which are connected respectively to said terminal and to said reference potential and in which the output from said second cascode configuration is connected to the transistor in said first amplifier which corresponds to the transistor in said second amplifier other than the one of said two transistors to which said output from said first cascode configuration is connected to said second amplifier.

28. A gyrator circuit comprising two amplifiers circularly connected, one to apply output signals phase-reversed from its input to the input of the other and the other to apply signals of the same phase as its input to the input of the one, each amplifier comprising a first field effect transistor having a control input, a second field effect transistor of the same conductivity type as said first field effect transistor connected to the output of said first field effect transistor in a cascode configuration, a third field effect transistor of opposite conductivity type connected in drain-to-drain series to said second transistor, and at least one fourth field effect transistor connected in source-to-drain series with said first, second, and third transistors to limit source-to-drain to-drain current of said first, second, and third transistors.

29. The gyrator circuit as in claim 28 in which said at least one fourth transistor comprises one field effect transistor of the same conductivity type as said third transistor connected to said third transistor in cascode configuration.

30. The gyrator circuit as in claim 28 in which said at least one fourth transistor comprises one transistor of the same conductivity type as said first transistor directly connected in source-to-drain connection with said first transistor and another transistor of the same conductivity type as said third transistor directly connected in source-to-drain connection with said third transistor, the connection between said two amplifiers being from the junction of said second and third transistors of each amplifier to the control input of the other amplifier.