CONVERTER FROM PULSE CODE MODULATION TO DELTA MODULATION

• US 3,772,678 A
• Filed: 05/22/1972
• Issued: 11/13/1973
• Est. Priority Date: 06/10/1970
• Status: Expired due to Term

• Current Assignee: Michel Villeret, Pierre A. Deschenes
• Original Assignee: Michel Villeret, Pierre A. Deschenes
• Inventors: Deschenes, Pierre A., Villeret, Michel
• Primary Examiner(s): Sloyan, Thomas J.
• Application Number:
  US05/255,811
• Time in Patent Office: 540 Days
• Field of Search: 3K/1300 325/38B 179/15AP,15AV 235/92 332/9R,9T,11D 340/347DD
• US Class Current: 341/75
• CPC Class Codes: H03M 7/3048 Conversion to or from one-bit differential modulation only, e.g. delta modulation [DM] H03M7/3004 takes precedence

Abstract

The system for the conversion of a PCM modulation signal into a Delta M modulation signal comprises: first register means for storing an input signal consisting of m binary digits representing the value x of the quantized signal at the end of a regular PCM modulation sampling period Ti; a '"'"''"'"''"'"''"'"'digital integrator'"'"''"'"''"'"''"'"' for storing the value e of the quantized signal at the end of sampling period Ti 1; a comparator connected to the first register means and to the digital integrator for comparing the value of the quantized signal x stored in the first register means with the value of the quantized signal e stored in the digital integrator and for generating a positive binary output signal Z if x is larger than e and a negative output signal Z if x is smaller than e; and second register means connected to the comparator for storing said output signal which is representative of the Delta M modulation signal.

Claims

1. A system for the conversion of a pulse code modulation signal into a delta modulation signal comprising:

a. an expander for converting a seven or eight binary digit pulse code modulation signal originating from a pulse code modulation link into a m binary digit input signal;

b. first register means connected to the output of said expander for storing said input signal consisting of m binary digits and representing the value x of the quantized signal at the end of a regular PCM modulation sampling period T1;

c. a digital integrator for storing the value e of the quantized signal at the end of sampling period Ti 1 ;

d. a comparator connected to the outputs of said first register means and of said digital integrator for comparing the value of the quantized signal stored in said first register means with the value of the quantized sigNal stored in said digital integrator and for generating a positive binary output signal Z if x is larger than e and a negative output signal Z if x is smaller than e; and

e. second register means connected to the output of said comparator for storing the output signal which is representative of the the delta modulation signal.

2. A system as defined in claim 1, for use with a delta modulator of the single integration type, wherein the m-3 less significant digits of said input signal are null thus reducing the number m of significant binary digits in the input signal to three digits representing the amplitude of the signal and one digit representing the sign of said amplitude, said expander comprising an input register having storage elements for storing the amplitude of said pulse code modulation signal, an output register having three storage elements for storing said most significant digits, a first gate circuit responsive to predetermined combinations of binary digits in the input register for identifying the group to which said input signal belongs and for storing the digits identifying said group into predetermined storage elements of said output register, a second gate circuit interconnecting predetermined storage elements in said input register to predetermined storage elements in said output register and responsive to said first gate circuit for transferring the binary digit relating to the level of the binary digits stored in said input register into the predetermined storage elements of said output register.

3. A system as defined in claim 2, wherein said comparator comprises a first gate circuit for comparing the difference between the absolute values of the amplitude of the signal x stored in the output register of said expander with the amplitude of the signal e stored in said digital integrator and for generating a signal S 1 if x is larger than e and S 0 if x is smaller than e.

4. A system as defined in claim 3, wherein said comparator further comprises a second gate circuit responsive to the sign of the signal stored into the output register of said expander, to the sign of the signal stored in said digital integrator, and to said signal S for generating said output signal Z.

5. A system as defined in claim 4, further comprising a memory device interconnecting said comparator to said digital integrator and to said second register means for temporarily storing the value of said signal Z before transferring said signal Z to said digital integrator and to said second register means.

6. A system as defined in claim 1, for use with a delta modulator of the double integration type, wherein said digital integrator comprises a first stage of integration and a second stage of integration.

7. A system as defined in claim 6, wherein the m-5 less significant digits of said input signal are null thus reducing the number m of significant digits in the input signal to five digits representing the amplitude of the signal and one digit representing the sign of the amplitude, and wherein said expander comprises an input register having storage elements for storing the amplitude of the signal originating from the pulse code modulation link and an output register having five storage elements for storing said five most signficant digits, a first gate circuit responsive to predetermined combination of binary digits in the storage elements of said input register for identifying the group to which said signal belongs and for storing digits identifying said group into predetermined storage elements of said output register, a second gate circuit interconnecting predetermined storage elements in said output register and responsive to said first gate circuit for transferring the binary digits relating to the level of the signal in said input register into the predetermined storage elements of said output register.

8. A system as defined in claim 7, wherein said comparator comprises a first gate circuit for comparing the difference between the absolute value of the amplitude of the signal x stored in the output register of the expander with the amplitude of the signal e stored in the second stage of integration of said digital integrator and for generating a signal S 1 if x is larger than e and S 0 if x is smaller than e.

9. A system as defined in claim 8, wherein said comparator further comprises a second gate circuit responsive to the sign of the signal stored in the output register of said expander, to the sign of the signal stored in the second stage of integration of said digital integrator, and to said signal S for generating said output signal Z.

10. A system as defined in claim 9, further comprising a memory device interconnecting said comparator to said ditigal integrator and to said second register means for temporarily storing the value of said signal Z before transferring said signal Z to said digital integrator and to said second register means.