CROSS CORRELATOR

• US 3,777,133 A
• Filed: 01/24/1972
• Issued: 12/04/1973
• Est. Priority Date: 01/26/1971
• Status: Expired due to Term

• Current Assignee: Colin Norman Wormald, Gerald Musgrave, Maurice Sidney Beck
• Original Assignee: Colin Norman Wormald, Gerald Musgrave, Maurice Sidney Beck
• Inventors: Beck, Maurice Sidney, Musgrave, Gerald, Wormald, Colin Norman
• Primary Examiner(s): Gruber, Felix D.
• Application Number:
  US05/220,017
• Time in Patent Office: 680 Days
• Field of Search: 235/181,151.34 343/1CL,112R,112D 324/77G,77H
• US Class Current: 708/425
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00

Abstract

Apparatus for cross-correlating a pair of electrical signals in which each signal is converted into a binary signal and fed to a feedback shift register. One of the registers has a delay in its feedback path. When the registers are full, the shift registers are continuously recycled and their outputs continuously compared by an exclusive - NOR gate. A counter coupled to the exclusive NOR gate counts the number of coincidences in a single cycle of the contents of the shift registers. This count is compared with the highest count attained in a previous cycle, the new count being held in a count store if higher than the previous highest count. The time between the start of the comparison and the time at which the highest count is obtained is stored in a separate time store. After each cycle the delay between the signals increases by one clock pulse. The time store then gives the delay for maximum correlation. In a further embodiment the invention operates with signals having three or more discrete levels in place of binary signals.

Claims

1. Apparatus for cross-correlating a pair of electrical signals, comprising shift registers associated with respective signals and each adapted to store a series of signal elements, the signal elements in each series representing the magnitude of the associated signal at succeeding instants in time, respectively, comparator means for comparing the signal element at the output stage of one shift register with the signal element at the output stage of the other shift register and producing an output signal representing correspondence between the two elements, accumulator means for accumulating output signals from the comparator means, control means for supplying shift pulses to each shift register so that each element in the register is advanced to the succeeding stage therein, feedback means for each shift register, each feedback means coupling the output stage of the associated register to the input stage thereof, one of the feedback means including a delay, whereby the application of a number of shift pulses corresponding to the number of stages in each register causes a cycle of operation in which the elements stored in one shift register are returned to their original stages in the register and the elements in the other shift register are displaced by at least one stage relative to their original stages, the control means supplying shift pulses to cause a series of succeeding cycles of operation resulting in a progressively increasing displacement of the elements in one register relative to the elements in the other register, and the accumulator means providing, for each cycle of operation, a signal representative of the number of output signals from the comparator means, and hence the degree of cross-correlation between the two electrical signals for a time delay corresponding to that cycle.

2. Apparatus as defined in claim 1 wherein the control means are adapted to supply shift pulses at a relatively high frequency for the purpose set forth, or to supply shift pulses at a relatively low frequency for clocking said pair of signals into said shift registers prior to the cyclical application of the elements stored therein to said comparator means, and the control means includes means responsive to a predetermined number of elements having been fed into said shift registers to supply shift pulses at said relatively high frequency and means responsive to a predetermined number of cycles having taken place to supply pulses at said relatively low frequency.

3. Apparatus as defined in claim 1, further including a first store connected to said accumulation means for storing said signal;

a second comparator connected to said first store and said accumulation means for indicating when the signal of the accumulation means is greater than the signal preserved in the first store;

the second comparator including means responsive to such indication at the end of a cycle to cause the signal of said accumulation means to be entered into said first store in place of the total signal preserved therein; and

means responsive to such indication being present at the end of a cycle to record the time delay between said pair of signals for such cycle.

4. Apparatus as defined in claim 3 wherein the last-named means comprises a counter connected to count the number of cycles and a second store, and is responsive to said indication to enter the cycle number in said counter into said second store.

5. Apparatus as defined in claim 1, further comprisinG a respective polarity detector for each of said pair of signals for converting the signals from an analog form into a binary form for supplying to said shift registers.

6. Apparatus as defined in claim 1, further comprising means for converting said pair of signals from an analog form into a form having at least two discrete levels.